Engineer II - Validation

Microchip•San Jose, CA

7d•Onsite

About The Position

Microchip Technology Inc. is seeking an Engineer II - Validation to join their FPGA Business Unit. This role involves creating systems level designs using FPGAs to bring up and debug use models in the lab. The candidate will be responsible for architecture definition, FPGA design creation, and developing validation plans for new and existing silicon products. This position requires an understanding of hardware architectures, defining use models, and executing system-level design implementations. The role also involves writing and maintaining Verilog, VHDL, and C code, supporting regression and re-use, and learning new system designs and validation methodologies. Collaboration with cross-functional teams, process improvement, and adherence to quality metrics are essential. The role may require late-night or early-morning calls to interface with engineers in the India Standard Time zone.

Requirements

Bachelors in EE/CE with 2.5+ years of experience.
Industrial experience of FPGA architectures is a must.
Possess an understanding of hardware architectures, system level IC design implementation, and knowledge of how to create end use scenarios.
Industrial experience in designing with RTL coding in Verilog or VHDL is a must.
Industrial experience in using Simulation (ModelSim or Synopsys or Cadence) and Synthesis (Synplicity or Xilinx or Altera) tools.
Industrial experience in silicon validation, failure analysis and debug.
Industrial experience in embedded firmware development and bringup in the lab.
Industrial experience in board level debug capabilities in lab environment: hands-on troubleshooting skills for digital logic and analog circuit on PCBs using oscilloscopes, digital analyzers, protocol exercisers and analyzers, FPGA integrated logic analyzers (e.g. Synopsys Identify, Xilinx Chip scope, Altera Signalscope, Lattice Reveal).
Good knowledge of validating system level designs based on embedded processors and peripherals such as SPI, I2C, UART, Ethernet, PCI and USB.
Strong commitment to quality and customer satisfaction.
Excellent verbal and written communication skills.
Able to travel 0-2 times annually if required.

Nice To Haves

Masters Degree in EE/CE
C, C++ or object-oriented programming skills is desirable.
Knowledge of RISC-V architecture and Instruction Set is desirable.
Knowledge of PERL/TCL/python scripting is desirable.
Knowledge and experience in JTAG, SVF and 1532 standards and STAPL programming is desirable.
Familiarity with any high speed SERDES controllers that make use of 12Gbps PCS, PMA is a big plus
PCIe Gen1/2/3
Ethernet 10/100/1000 Mbps : Triple Speed Ethernet MAC
Ethernet 1/2.5/10G [RGMII, (Q/)SGMII, USXGMII]
Ethernet IEEE702.3dm
Ethernet Sync-E (Synchronous Ethernet), Time Sensitive Networks
Video interfaces SDI-SD/HD/3GHD and SDI (5.94, 11.88Gbps), Displayport (6.48 to 10Gbps), HDMI (3.96 to 6 Gbps), HBR3(8.1 Gbps), MIPI C-PHY & D-PHY 1Gbps/lane
Design and debug experience for any of the below high-speed serial communications protocols is a plus: USB 3.1,3.2 CoaXpress (12.5G) CXP(10G) OctalSPI I3C, PMBUS, I2S CAN
Miscellaneous: Embedded Non-Volatile Memories
DDR3/DDR4/LPDDR4

Responsibilities

Use FPGAs to create systems level designs to bring up and debug use models in the lab.
Architecture definition and FPGA design creation utilizing all hardware features and IP cores targeted to existing and future Microchip products.
System and FPGA design must exercise all the use models targeted for each product mimicking end applications in a customer setting.
Develop high level system and product level validation plans for new and existing silicon products and projects, execute per plan.
Review dependencies, estimate effort and identify and communicate risk.
Understand hardware architectures, define use models and execute / oversee system level design implementations required to utilize the silicon features.
Be an effective contributor in a cross-functional team-oriented environment.
Write high quality code in Verilog, VHDL and C code.
Maintain existing code.
Support regression and re-use.
Learn new system designs and validation methodologies.
Understand FPGA architectures.
Collaborate with cross-functional managers/teams to identify and resolve inter-dependencies.
Define and improve processes followed in the department; follow quality metrics and assess per project.
Willing to take late night or early morning calls to interface with engineers working in India Standard Time zone, when and if required.