Engineer I-Design (ASIC)

Microchip Technology Inc.•San Jose, CA

3d•Onsite

About The Position

Microchip Technology Inc. is a leading provider of embedded control applications. Our product portfolio comprises general purpose and specialized 8-bit, 16-bit, and 32-bit microcontrollers, 32-bit microprocessors, field-programmable gate array (FPGA) products, a broad spectrum of high-performance linear, mixed-signal, power management, thermal management, radio frequency (RF), timing, safety, security, wired connectivity and wireless connectivity devices, as well as serial Electrically Erasable Programmable Read Only Memory (EEPROM), Serial Flash memories, Parallel Flash memories, and serial Static Random Access Memory (SRAM). We also license Flash-IP solutions that are incorporated in a broad range of products. Microchip Technology Inc. has a Engineer I - Design opening based in San Jose, CA. The successful candidate will be responsible for designing, simulating, and verifying various RTL-based blocks on our devices. Microchip’s designs are an SOC with various hard and soft IP blocks that support many industry standard protocols for Imaging, Networking System Connectivity, Compute and Data Storage.

Requirements

Bachelor’s in Electrical Engineering, Computer Engineering or Computer Science.
Design courses and practical application of course learning for high-speed RTL design.
Experience with RTL Design tools that include design entry, synthesis, formal verification, RTL/gate level simulation, cross-domain clocking analysis and static timing analysis.
Course and Practical usage in RTL design, design verification, synthesis & formality.
Proficiency in SystemVerilog development languages.
Course and Practical usage in Static Timing Analysis and Verilog simulation tools.
Should be able to design complex state machines & data path logic.
Proficiency in scripting languages (TCL / Perl / Python) and LINUX.
Ability to understand and implement industry standards.
Ability to write detailed design specifications.
Good analytical, oral and written communication skills.
Able to write clean, readable presentations.
Self-motivated, proactive team player.
Ability to work to schedule requirements.

Nice To Haves

Master’s in Electrical Engineering, Computer Engineering or Computer Science.
FPGA and ASIC System On Chip Design Experience.
Lab Experience for system-level validation.

Responsibilities

General RTL and ASIC development
Detailed module design, performance analysis and detailed design specification creation.
Participate in the RTL implementation, synthesis, simulation, pre-layout/post-layout timing verification.
Understanding of emerging high speed design techniques to improve Data & Command processing bandwidth, reduce latencies & increase reliability.
Support porting the design into test chips and emulation platforms – experience with FPGA design and board implementation tools is advantageous.