Engineer - FPGA

AIRBUS U.S. Space & Defense, Inc.•State College, PA

16h•Hybrid

About The Position

Airbus U.S. Space & Defense, Inc offers advanced solutions to meet the most complex U.S. defense, security, space, and intelligence requirements. Celebrating over 50 years in the US, we remain a trusted government partner, leveraging world-class satellite, laser communication, rotor and fixed wing solutions to help our national security, defense and space focused customers meet their missions. Airbus U.S. looks to employ a commitment driven team, dedicated to enabling our customer's mission success. We are committed to maintaining a diverse and inclusive work environment and a welcoming and engaging staff. With competitive compensation and superior employee benefits, as well as a commitment to fostering individual career growth, Airbus U.S. is the place where top talent wants to work. Position Summary: Airbus U.S. is looking for an enthusiastic and creative FPGA engineer to develop digital logic solutions for our custom hardware on satellites. We're looking for candidates who can bring exceptional skills to accelerate our small-satellite avionics development program.

Requirements

Bachelor's degree in STEM (Science, Technical, Engineering, Math) or related areas.
A minimum of 3 years of experience with FPGAs with a bachelor's degree, or 1 year with a master's degree.
Academic and/or internship experience with FPGAs may be considered in lieu of industry work experience.
Proficiency in coding structural and behavioral architectures in hardware description languages such as VHDL, Verilog, or System Verilog.
Familiarity with FPGA design tools from AMD Xilinx Vivado and Microchip Libero, including SoC block diagram integration and third-party IP utilization.
Experience in digital logic verification via simulation using the Vivado simulator, ModelSim ME, or cocotb.
Proficiency in the use of Git for source code revision control.
Experience with programming for hardware verification and validation, including C, C++, and Python.
Strong understanding of best practices for synchronous logic design.
High proficiency in oral and written technical communication.
US Citizenship is required.
Ability to obtain and maintain a U.S. Government security clearance.

Nice To Haves

Familiarity with standard mitigation techniques for radiation induced single-event upsets is a plus.
Active U.S. DoD security clearance at Secret or above highly desirable.

Responsibilities

Contribute to FPGA design and development for Airbus U.S.'s next-generation of small-satellite avionics.
Be heavily involved in the process of FPGA design architecture, initial board bring-up, debugging, testing, requirements verification, and design revisioning across the hardware development life cycle, from prototyping to production.
Utilize design and quality requirements, electrical schematics, and parts datasheets to architect, develop, and document FPGA solutions for control and dataflow applications in small satellite avionics.
Develop and verify VHDL RTL and top-level block diagram solutions for FPGA SoCs.
Create FPGA device constraints, perform logic synthesis, execute place and route, and generate FPGA device images in the Vivado and Libero design environments.
Perform static timing analysis and achieve timing closure, generate and verify compilation reports, and disposition compilation warnings.
Document design architecture, software interfaces, and compilation results.
Support laboratory-based testing, troubleshooting, and performance characterizations of FPGA designs on development kits and custom hardware solutions.
Develop test scripts and software for embedded Linux and bare-metal platforms to validate hardware function and performance during board bring-up, debugging, and testing.
Support hardware architecture development, including reviewing selected FPGA devices for fitness to their intended applications and estimating resource utilization and power dissipation.
Provide an FPGA-based review of electrical schematics and PCB designs, including pin assignments, clock generation, reset distribution, and high-speed interfaces to memories and transceivers.
Support make-vs-buy trade studies for licensing third-party IP cores.
Support board-level and unit-level design reviews.
Support systems engineering and cross-disciplinary development efforts.