Emulation Engineer

MatX•Mountain View, CA

84d•$120,000 - $600,000•Hybrid

About The Position

MatX is building the compute platform for AGI, developing vertically integrated full-stack solutions from silicon to systems, including hardware and software, to train and run the largest ML workloads for AGI. We are seeking Emulation engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Successful candidates will be responsible for delivering performant and functionally accurate silicon for MatX products across compute, memory management, high-speed connectivity, and other key technologies. We're hiring a Senior/Staff Emulation Engineer to build the infrastructure, flows, and debug methodology behind our advanced connectivity SoCs. This role sits in the Emulation team but has a broader impact, creating reusable flows that span emulation, SoC simulation, firmware/software bring-up, and post-silicon validation. We are looking for a multi-disciplinary engineer with an out-of-the-box, can-do mindset, comfortable moving between RTL, software, tooling, system debug, and vendor flows. Expertise in every area is not required, but a reuse-first mindset, strong software instincts, and the ability to learn quickly across boundaries are essential.

Requirements

Strong hands-on experience with SoC emulation or system-level validation.
Experience with at least one commercial emulation platform, such as Palladium.
Working Verilog/SystemVerilog and waveform-debug skills — enough to develop a custom transactor or agent when needed (with or without AI assistance). Deep RTL design expertise is not required.
Strong software and automation skills — Python plus one or more of C, C++, Rust, Tcl, or shell.
Demonstrated ability to build tools and infrastructure, not just run existing flows.
Strong system-level debug instincts spanning RTL, firmware, and software.
Ability to work independently and across functional and team boundaries.
All candidates must be authorized to work in the United States and work from our offices in Mountain View Tuesdays-Thursdays.
This position requires access to information that is subject to U.S. export controls. This offer of employment is contingent upon the applicants capacity to perform job functions in compliance with U.S. export control laws without obtaining a license from U.S. export control authorities.

Nice To Haves

UVM or hybrid SoC testbench development.
Integrating cycle-accurate, software, or reference models into emulation/DV flows.
Rust in verification or emulation flows (or strong interest in adopting it).
Bazel or large-scale build/regression systems.
Reusable stimulus across simulation, emulation, and post-silicon.
AI/LLMs used to build real engineering tools — debug, triage, flow generation — beyond chat prompting.
Connectivity SoCs, PCIe/CXL, Ethernet, DMA, HBM/memory subsystems, chiplets, or interconnect fabrics.
Firmware or driver bring-up on emulation platforms.
Scaling emulation or verification infrastructure across multiple projects or product lines.

Responsibilities

Define and execute emulation strategy and test plans for complex connectivity SoCs.
Bring up and debug large-scale models on commercial emulation platforms such as Cadence Palladium, Zebu or Veloce.
Integrate external components such as SpeedBridge and VirtualBridge adapters, Accelerated VIP, and memory models — for PCIe, HBM4, Ethernet, AXI/AMBA, JTAG, and (Q)SPI. Build custom transactors where needed.
Develop HW/SW co-emulation and co-simulation flows using RTL, software/reference models (Rust, C/C++, SystemC), firmware, and software tests.
Build reusable transactors, agents, stubs, bridges, checkers, and acceleration flows — including developing new transactors and agents from scratch when off-the-shelf options don't fit.
Drive emulation speed-ups and resource utilization — compile-time reduction, partitioning, clocking strategy, regression scheduling, multi-user capacity, and waveform/trace management.
Build automation for regression triage, debug, model usability, and engineering productivity.
Go beyond prompting with AI — build practical LLM-based tooling for log analysis, waveform triage, debug assistance, and flow generation, including custom skills, agents, rules, and workflows that fit our engineering stack.
Collaborate with architecture, RTL, DV, SoC, firmware, driver, kernel, validation, and EDA/vendor teams.

Benefits

Company subsidized Health, Dental, Vision, and Life insurance
Pre-tax Health Savings Accounts with generous company contribution
4 weeks paid time off (accrued)
12 company holidays
3 weeks remote/flexible work per year
Up to 12 weeks of paid parental leave, regardless of your path to parenthood
$1,500 yearly towards your professional development e.g. conferences, courses, and other learning opportunities
Team Lunches, quarterly off-sites, and regular town halls
401K and/or Roth IRA, with 5% company contribution
Pre-tax spend accounts for medical, dental/vision, dependent care, parking, and transit expenses
Commute on company card/Uber account or reimburse train rides
$50 per month to use on the perks you care about most
Home-tech setup, and remote wifi expense reimbursement
100% paid mental health benefit via SpringHealth and Guardian EAP
10 weeks pregnancy disability leave
flexible return-to-work hours
Benepass reproductive health & parental benefit
Up to $20K/month plus a dedicated internal AI Tooling Team to support your productivity