Embedded SoC Architect

Advanced Micro Devices, Inc•San Jose, CA

4d•Hybrid

About The Position

The AMD Adaptive Embedded Computing Group is looking for a Senior SoC Architect to join the team in defining the next generation of Adaptive and Embedded SoCs. You will drive novel SoC architecture solutions across a wide range of applications, including Embedded Computing, AI/ML, Data Center, Communications, Automotive, and Aerospace, in close collaboration with customers, partners, product planning, SoC and IP architects, and design & verification teams.

Requirements

Technical background architecting SoC, processor, accelerator and I/O subsystems.
Technical knowledge of Cores running either x86, RISC-V, or ARM ISA, I/O protocols such as PCIe and Ethernet, and how SoCs are architected to integrate across the various subsystems, including DDR.
Expertise in at least one of the domains such as embedded computing, aerospace & defense, data-center, networking, or automotive industries.
BS/MS/PhD in electrical or computer engineering or related field.

Nice To Haves

Knowledge of ARM Processors and AXI Interconnects desired.
Knowledge of FPGA and AI/ML Accelerators desired.
Knowledge of boot, security, debug, telemetry and RAS desired.

Responsibilities

Responsible for driving low-power, cost-optimized SoC architectures with processor, accelerator and I/O subsystems.
Define SoC architectures with internal embedded processor-subsystems, Network on Chip, Memory controllers, and FPGA fabric.
Create flexible and modular subsystem architectures that can be deployed in either chiplet, monolithic or 3D form factors.
Work with customers, and cross-functional teams to scope SoC requirements, analyze PPA tradeoffs, and then define architectural requirements that meet the PPA and schedule targets.
Define hardware, software, and firmware interactions between embedded processing subsystems, hardware accelerators, and external CPUs.
Author architecture specifications in clear and concise language. Guide and assist pre-silicon design/verification and post-silicon validation during the execution phase.