Embedded Firmware Engineer

V2X•Indianapolis, IN

About The Position

V2X is seeking a talented Embedded Firmware Engineer to join our Embedded Solutions team within the Engineering Solutions organization. Embedded Solutions is a cross‑disciplinary core function dedicated to the design, development, and integration of secure, high‑performance embedded systems that enable mission‑critical defense and aerospace applications. In this role, you will play a key part in the full lifecycle development of advanced FPGA‑based solutions, including RTL design, simulation, synthesis, and integration on custom and COTS hardware platforms. You will work collaboratively with experienced engineers in a multidisciplinary, matrixed environment emphasizing technical rigor, collaboration, and continuous learning. This position is ideal for motivated early‑career engineers seeking to expand their impact across FPGA logic design, high‑speed digital interfaces, and hardware‑software integration.

Requirements

Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related STEM field.
Approximately 2–5 years professional experience in FPGA or digital logic design (hands‑on academic, internship, or professional work considered).
Proficient with VHDL and/or Verilog for synthesizable RTL design targeting FPGAs.
Experience with at least one major FPGA toolchain (e.g., Xilinx Vivado/Vitis, Intel Quartus, Microchip Libero) for synthesis, implementation, and bitstream generation.
Experience with lab‑based troubleshooting and board bring‑up, including use of oscilloscopes, logic analyzers, or similar tools for FPGA/hardware integration.
Familiarity with version control and configuration management tools (e.g., Git, Azure DevOps).
Effective communication skills, strong team orientation, and commitment to continuous technical growth.
U.S. citizenship required.
Ability to access systems with information restricted to U.S. citizens as required by federal contract guidelines.
Eligibility to obtain and maintain a U.S. Department of Defense (DoD) security clearance may be required for certain projects.

Nice To Haves

Experience developing timing constraints and supporting timing closure for FPGA designs.
Exposure to high‑speed digital interfaces (e.g., DDR, LVDS, SERDES, PCIe, Ethernet) and related SI/PI considerations.
Familiarity with on‑chip debug tools (e.g., Xilinx ILA/ChipScope, Intel SignalTap).
Experience collaborating with embedded firmware/software teams on register maps, drivers, and HW/SW integration.
Exposure to scripting for build/test automation or tooling—Python, TCL, or similar preferred.
Knowledge of relevant industry standards and practices (e.g., DO‑254, DO‑178C, MIL‑STD interfaces, or similar aerospace/defense standards).
Experience collaborating in Agile or SCRUM‑based development teams.

Responsibilities

Design, implement, and validate FPGA logic solutions using VHDL and/or Verilog, targeting modern FPGA platforms (e.g., AMD/Xilinx, Intel, Microchip).
Develop and integrate FPGA‑based interfaces and processing pipelines for serial buses, memory interfaces, LVDS, and other high‑speed or control I/O.
Create and execute simulation testbenches (e.g., ModelSim/Questa or similar) to verify functional correctness, and support debug using waveform analysis and on‑chip debug tools (ILA/SignalTap).
Contribute to timing constraint development and timing closure, working with senior engineers to meet performance, clocking, and resource‑usage requirements.
Support hardware bring‑up, board‑level verification, and troubleshooting, using oscilloscopes, logic analyzers, and related lab tools in collaboration with electrical, firmware, and systems engineers.
Participate in system‑level integration and verification, ensuring FPGA designs interoperate correctly with embedded processors, firmware, and external devices.
Prepare and maintain clear technical documentation, including design descriptions, interface definitions, constraint files, and test logs in accordance with V2X processes.
Participate in Agile development teams—collaborate via MS Teams, Azure DevOps, and shared digital environments to deliver disciplined, high‑quality engineering outcomes.
Engage in peer code and design reviews, share lessons learned, and support continuous improvement in product quality, safety, and engineering practice. Maintain a strong focus on disciplined execution, safety, quality, and compliance with industry and secure‑development practices.