Electro-Optical Interconnect Packaging Development Hardware Engineer (Onsite)

Cisco•San Jose, CA

2d•$165,000 - $241,400•Onsite

About The Position

The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms—like Silicon One—are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world. Cisco Silicon One (#CiscoSiliconOne) is a business organization with a long track record of building complex and high-performance Silicon ASICs. Our silicon devices drive the world’s most complex networks and carry over 90% of IP traffic. Cisco Silicon One is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. We are a highly specialized ASIC team with experts in all aspects of advanced IC package design and heterogeneous system integration. Our substrates use the latest 2.5D fanout technologies for large-scale integration, using the latest signaling and data transfer technologies. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry! As an Interconnect Packaging Development Engineer within the Silicon Core team, you will operate at the intersection of advanced packaging technology and strategic execution. You will be a key member of the platform development team responsible for designing, qualifying, validating, and debugging critical packaging technology building blocks, processes, and tools that support Cisco’s cutting-edge Silicon One ASIC roadmaps. In this highly collaborative role, you will partner with design engineering, operations, and supply chain teams to innovate next-generation technologies, including co-packaged optics and co-packaged copper. You will also engage directly with external OSATs, Fabs, contract manufacturers, and key suppliers to drive validation and problem-solving efforts.

Requirements

Bachelor's degree in Electrical Engineering and 7+ years of relevant experience, or Master's degree in Electrical Engineering and 4+ years of relevant experience, or PhD in Electrical Engineering and 1+ years of related experience, or equivalent related work experience.
7+ years of hands-on laboratory experience with precision measurement equipment.
Proven experience with high-frequency Vector Network Analyzers (VNA), S-parameter probe measurements, and high-frequency calibration methodologies.
Experience with sample preparation (cross-sectioning, polishing, potting) and operating SEM/EDS systems for failure analysis.

Nice To Haves

Demonstrated ability to work collaboratively, independently, and safely in a lab environment with highly sensitive devices under test (DUTs).
Strong working knowledge of SI/PI simulation suites, including Ansys HFSS, Siwave, Q3D, and Keysight Pathwave ADS.
Hands-on experience conducting thermal analysis using the Fabry Perot Resonator to measure Dielectric Loss, Dielectric Constant, and surface roughness.
Deep knowledge of SI calibration and test flows for both fixtured and micro-probing configurations up to mmWave frequencies (including TDR).
Hands-on experience with optical spectrum analyzers (OSA), optical frequency domain reflectometry (OFDR), optical benches, and fiber probes.
Working knowledge of 3D CAD generation (Autodesk Fusion), 3D printing, and basic machining/fabrication (milling, CNC instruments) to generate custom fixtures.
Experience proactively engaging with test infrastructure vendors to assess roadmaps, define requirements, coordinate procurement, and lead tool bring-up.
A strong willingness to continuously learn and evolve professionally across mechanical, thermal, and material science domains.

Responsibilities

Perform comprehensive Signal and Power Integrity (SI/PI) analysis and modeling using simulation tools including Ansys HFSS, Siwave, Q3D, and Keysight Pathwave ADS.
Define and specify advanced IC packaging test vehicles designed to provide empirically derived data for SI/PI tool verification.
Provide rigorous model verification by synchronizing simulation models with physical, measured data to ensure high-fidelity predictive modeling.
Conduct thermal analysis using tools like TMA, DMA, TGA, or DSC to evaluate laminate properties (e.g., Tg, CTE, outgassing).
Perform Fabry Perot dielectric and Copper material characterization, matching empirical measured data to simulation. Generate and deliver frequency-dependent IC-packaging dielectric material models over temperature for use in simulation tools.
Conduct hands-on reliability and material qualification testing to proactively identify and mitigate risks, resolving complex packaging issues.
Support quality investigations by performing root-cause failure analysis, executing material cross-sectioning, vacuum potting, polishing, and SEM/EDS imaging.
Utilize 3D CAD (Autodesk Fusion), 3D printing, and basic machining (CNC milling) to design and fabricate custom fixturing solutions to address immediate lab measurement challenges.
Develop technical requirements for advanced packaging, build measurement-driven databases to correlate thermo-mechanical and electro-optical impacts, and collaborate with test infrastructure vendors on tool procurement and bring-up.

Benefits

medical, dental and vision insurance
a 401(k) plan with a Cisco matching contribution
paid parental leave
short and long-term disability coverage
basic life insurance
10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees (non-exempt)
flexible vacation time off program (exempt)
80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
Optional 10 paid days per full calendar year to volunteer
annual bonuses (for non-sales roles)
performance-based incentive pay (for sales roles)