In this role, the layout engineer will closely work with the analog design team to layout and verify custom analog/mixed-signal IPs. This includes leading full-custom IC layout design and verification, chip floor planning, analog IP layout, and chip-level layout integration of various analog, mixed-signal, and ASIC blocks. The role involves full verification of block-level and top-level layouts, including extraction, DRC, LVS, and DFM checking. The engineer will also be responsible for layout schedule planning, collaborating with other IP layout engineers for integration, co-working with designers on floor planning, and performing layout reviews for power/ground routing, electromigration, signal path checks, matching, and signal coupling.
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Job Type
Full-time
Career Level
Mid Level