Electrical Design and Analysis Engineer 5

The Structures Company•El Segundo, CA

13h•$115•Onsite

About The Position

This role involves inheriting FPGA top-level design, creating new functional blocks and interfaces, and integrating third-party and in-house IP cores. The engineer will update constraint files, perform synthesis, simulation, and Place & Route processes to ensure timing closure and design integrity. Programming FPGA devices, primarily from Xilinx Versal, Ultrascale, and Ultrascale+ families, is a key responsibility. The position requires collaboration with the system engineering team for hardware and software system integration and support for testing activities to deliver a fully functioning system. The engineer will apply Verilog and SystemVerilog HDL for FPGA design and implementation using Xilinx and AMD Vivado, and perform advanced FPGA implementation including synthesis, timing closure, and constraints management. Producing high-quality technical documentation for FPGA designs is also expected.

Requirements

Active Secret Security Clearance required to start.
Must be a U.S. Person (as defined by ITAR).
Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, computer science, mathematics, physics or chemistry (e.g. Bachelor) and typically 14 or more years' related work experience (e.g. PhD+9 years' related work experience, Master+12 years' related work experience).
5+ years of FPGA and or ASIC design experience.
Strong Xilinx and AMD Vivado experience.
Experience with Versal family devices.
Verilog and SystemVerilog HDL proficiency.
Advanced FPGA implementation skills including synthesis, timing closure, and constraints.
Active U.S. security clearance.

Nice To Haves

2+ years of FPGA design experience.
Strong Xilinx and AMD Vivado experience.
Verilog and SystemVerilog proficiency and advanced FPGA implementation skills.

Responsibilities

Inherits FPGA top-level design and creates new functional blocks and interfaces.
Integrates third‑party and in‑house IP cores into the FPGA design.
Updates constraint files and performs synthesis, simulation, and Place & Route processes to ensure timing closure and design integrity.
Programs FPGA devices primarily from Xilinx Versal, Ultrascale, and Ultrascale+ families.
Collaborates with system engineering team to support hardware and software system integration.
Supports testing activities to deliver a fully functioning system.
Applies Verilog and SystemVerilog HDL for FPGA design and implementation.
Uses Xilinx and AMD Vivado for FPGA development and implementation.
Performs advanced FPGA implementation including synthesis, timing closure, and constraints management.
Produces high‑quality technical documentation for FPGA designs.