Edge & Physical AI HW Product Manager/Director

NXP Semiconductors•Chandler, AZ

About The Position

Owns the multi-generational hardware roadmap for NXP’s edge and physical AI NPU portfolio, spanning discrete Ara-series NPUs, i.MX-integrated NPU IP, and chiplet-based scale-out architectures. The role translates customer requirements and competitive intelligence into silicon product specifications and drives product definition with silicon architects and engineering leads. It also owns product business cases and investment recommendations, and leads make-vs-buy-vs-license assessments for new capabilities and IP. The position defines chiplet strategy and NPU IP integration requirements in collaboration with related product teams, and drives customer early-access and sampling programs. It establishes competitive benchmarking and differentiation strategy, manages products from definition through ramp, sustaining, and end of life, and represents the portfolio to executives, customers, partners, and industry audiences. The role co-owns software development with the software product manager and develops end-to-end system solutions and demonstration platforms for developers.

Requirements

10+ years of product management or product strategy experience in semiconductor or silicon IP, with direct ownership of hardware product definition and roadmap.
Hands-on experience defining silicon product specifications, including performance targets, memory architecture, power envelopes, packaging, and process-node decisions.
Strong understanding of SoC and IP integration; experience defining IP for integration into a host processor or SoC is strongly preferred.
Track record of driving design wins and customer adoption across multiple product generations.
Ability to build and defend business cases, including BOM cost, ASP, gross margin, and market sizing.
Experience with competitive analysis and differentiation strategy in a fast-moving semiconductor segment.
Strong cross-functional leadership skills and ability to align architecture, engineering, sales, marketing, and executive stakeholders.
Excellent written and verbal communication skills, including ability to explain complex technical tradeoffs to engineering teams and executive audiences.

Nice To Haves

Familiarity with chiplet architectures and multi-chip interconnect standards such as UCIe or BoW, or equivalent.
Direct experience in AI/ML inference silicon, such as NPU, GPU, or inference accelerator product management.
Familiarity with edge inference workloads, including CNNs, transformers, LLMs, and VLM variants.
Experience working with ODMs, OEMs, and contract manufacturers on board design, system integration, and production.
Background in industrial, automotive, or embedded edge markets.
MBA or advanced degree in Electrical Engineering, Computer Engineering, or a related discipline.

Responsibilities

Define and maintain the multi-generational hardware roadmap across discrete Ara-series NPUs, i.MX-integrated NPU IP, and chiplet-based scale-out architectures.
Translate customer requirements and competitive intelligence into silicon product specifications, including performance targets, memory architecture, power, I/O, packaging, safety, and process-node decisions.
Drive product definition through architecture reviews, design partitioning, and feature tradeoffs with silicon architects and engineering leads.
Own business cases for hardware products, including BOM cost, ASP, gross-margin targets, volume projections, and NPV; present investment recommendations to executive leadership.
Lead make-versus-buy-versus-IP-license assessments for new capabilities, including MAC-array architectures, in-memory compute, memory subsystems, and interconnect IP such as UCIe.
Define chiplet strategy for scale-out NPU configurations, including die partitioning, die-to-die interface selection, and multi-chip package requirements.
Partner with i.MX, S32 SoC, i.MCU, and RT product teams to define NPU IP integration requirements, including power domains, bus interfaces, memory bandwidth allocation, software-hardware co-design constraints, SoC bring-up, and debugging.
Drive early-access and customer-sampling programs; gather validated requirements from lead customers and incorporate them into architecture decisions before design freeze.
Own the competitive benchmarking framework and differentiation strategy for NPU silicon, including performance, power, cost, safety, support, software ecosystem, and form factors.
Manage the product lifecycle from definition through ramp, sustaining, and end of life, including customer transition plans across generations.
Represent the NPU hardware portfolio to NXP executive leadership, customers, partners, and at industry events.
Co-own software development for discrete, integrated, and chiplet-based designs with the software product manager.
Develop end-to-end system solutions and demonstration platforms for hardware and software developers at industry events and conferences.