Edge Hardware / Firmware Engineer

Furientis•Los Angeles, CA

1d•Onsite

About The Position

America is critically deficient in production of defensive munitions- we currently produce shipborne interceptors in the few hundreds per year while our adversaries are producing offensive threats in the tens of thousands per year. Furientis was started to help solve this problem- introducing a new class of cost-effective, high production rate, interceptor missiles. We're seeking motivated individuals who internalize this problem and are eager to apply their past experience in similar industries (aerospace, defense, automotive/racing, robotics) and out of the box thinking to solve this problem for the US and its allies. About the Team The Seeker Team builds the eyes and the targeting logic of our weapon system: a low-cost, mass-producible, multimodal missile seeker that leans on commercial supply chains where they outperform the defense legacy, with supply-chain security engineered in from day one. On a modern missile, the seeker is 40 to 60% of unit cost and often drives overly long delivery cycles; accordingly, the seeker team is at the tip of the spear for delivering value to our customers and to the taxpayer. Seeker design has exactly two real constraints: physics and mission. Supply chain, vendor lead time, qualification cost, "the way it's always been done": none of that stops us. We are a small, deeply technical team that drives capability through ingenuity and bias for action and ships hardware that flies. This is a wear-many-hats environment where you must be comfortable "building the airplane in flight" and stepping well outside your comfort zone; a narrowly scoped role with clean handoffs is not what this team offers. This is an AI-native team. Through fluent use of cutting-edge agentic coding tools, one engineer here consistently out-delivers a much larger conventional team. You will have opinions about where these tools help and where they do not, provide governance input, and build AI into your workflow from day one. About the Role You will execute the design, layout, bring-up, and qualification of the boards and SoMs that make our seeker run: FPA and image-sensor interface, GPU SoC / SoM carrier, high-speed digital and low-noise analog signal chains, shared-memory data plane between sensor and compute, power architecture from missile bus to detector bias rails, and the low-level firmware that brings it all up. This is a hands-on role for an engineer who can take a design from blank schematic to first-light bring-up to a low-latency CUDA pipeline running on an SoM in days, not months, and who thinks about manufacturability and second-source risk before the first prototype is built.

Requirements

B.S. in Electrical Engineering, Computer Engineering, or related; M.S. preferred.
4 to 6 years of mixed-signal hardware and firmware bring-up experience, with responsibility for at least one board (ideally with an SoM carrier) from schematic through bench validation.
Strong fundamentals across high-speed digital (signal integrity, controlled impedance), low-noise analog, and power conversion.
Hands-on with high-speed image-sensor interfaces (LVDS, MIPI CSI-2, CameraLink, SLVS-EC, or SerDes) end-to-end from sensor to compute. Non-negotiable.
Production CUDA experience: shipped real CUDA code, not dabbled. Reasons about kernels, memory layout, occupancy, streams, and host-device transfer cost; at the level needed to debug a stalled pipeline on an Orin.
SoMs and shared-memory ecosystems (Jetson family or equivalent): zero-copy and unified-memory patterns, getting sensor data into GPU-accessible memory without copies you can't afford.
Experience or strong willingness to work in Rust and Python for firmware, drivers, bring-up tooling, and low-latency host-side code.
Hands-on TensorRT: model conversion, calibration, plugin integration, and deployment into a real on-board inference pipeline.
Low-latency, jitter-sensitive applications: deterministic timing budgets, real-time scheduling, interrupt and DMA latency analysis.
Schematic and PCB tooling proficiency (Altium, Cadence, or KiCad) with practical layout judgment.
Comfortable on the bench (scope, logic analyzer, soldering iron, rework).
AI-native working style: daily use of agentic coding tools (Claude Code, Codex, OpenCode, Kilo, or similar) for firmware, test-bench scripts, component selection, and schematic/layout review.

Nice To Haves

NVIDIA PVA, Qualcomm Hexagon, OpenCL, or other heterogeneous-compute runtimes beyond CUDA.
Direct experience interfacing to IR detectors, focal-plane arrays, or ROICs (cooled or uncooled).
Carrier-board design experience for a commercial SoM.
High-volume or DFM experience: walked a board through CM bring-up at production rate.
MIL-STD-461, MIL-STD-810, MIL-STD-1553, RS-422, or Ethernet-over-physical-layer qualification experience.
Direct missile, munition, ISR, or aerospace-qualified hardware program experience.

Responsibilities

Develop and bring up mixed-signal boards centered on a GPU SoC or SoM (NVIDIA Jetson/Orin, Qualcomm, NXP, or similar): high-speed image-sensor interface, low-noise analog, power conversion, and missile-bus IO.
Architect and implement the high-speed image-sensor interface (LVDS, MIPI CSI-2, CameraLink, SLVS-EC, SerDes) end-to-end from sensor pinout to SoM ingest, including timing, signal integrity, and zero-copy DMA into GPU-accessible memory.
Stand up the on-board compute path on GPU SoCs: CUDA pipelines, TensorRT inference, and shared-memory/zero-copy data movement from capture to inference, hitting hard latency and jitter budgets.
Write low-level firmware, drivers, and bring-up tooling in Rust and Python: device-tree, sensor configuration, board diagnostics, automated bench tests, and the on-the-wire serialization layer (protobufs or equivalent).
Execute schematic capture and PCB layout (Altium, Cadence, or KiCad), or partner with a layout designer when complexity warrants.
Carrier-board design for the chosen SoM as required.
Drive the power chain from missile bus to FPA bias rails (sequencing, low-noise LDOs, switching regulation, transient response, isolation), with component selection that bakes in cost, lead-time, second-source, and rad-tolerance from day one.
Bring up boards on the bench (scope, logic analyzer, BERT, thermal imaging, rework iron) and chase low-latency, jitter-sensitive timing bugs to their physical root.
Execute EMI/EMC qualification per MIL-STD-461 and environmental qualification per MIL-STD-810; partner with mechanical on conformal coating, staking, thermal interfaces, and survivability.
Bake DFM and DFT in from the start: CM engagement, ICT/AOI, board-level test fixtures, and a clear path to volume.