EDA Engineer (RFIC Engineering)

SpaceX•Irvine, CA

4h•$125,000 - $175,000•Onsite

About The Position

At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe. We are seeking a motivated, hands-on, proactive, and intellectually curious EDA Engineer to help support and improve the IC design environment used by silicon design, layout, verification, physical design, and methodology teams. The role focuses on keeping EDA tools reliable, PDK and flow usage reproducible, and designers productive across analog/RF/mixed-signal and digital silicon workflows. This is a growth-oriented role for an engineer with strong fundamentals in electrical engineering, computer engineering, computer science, Linux, scripting, or IC design tools. The engineer will partner design teams, other EDA engineers, IT/server teams, foundries, and EDA vendors to triage production issues, improve tool flows, build lightweight automation, maintain documentation, and convert repeated support issues into reusable methodology.

Requirements

Bachelor's degree in electrical engineering, computer engineering, or computer science
2+ years of experience in EDA/CAD support, IC design flow development, silicon design, physical verification, verification infrastructure, and/or CAD automation

Nice To Haves

Master’s degree in electrical engineering, computer engineering, computer science, or a related technical field; or equivalent practical experience
Hands-on experience using or supporting at least one major EDA flow, such as Cadence Virtuoso/Spectre, Siemens Calibre, Synopsys/Cadence digital tools, Keysight ADS, EMX/HFSS, or similar tools
Practical Linux and scripting experience with Python, shell, Tcl, Perl, Makefile, SKILL, or similar languages
Ability to independently triage well-scoped user issues, own small flow improvements, document resolutions, and escalate with clear evidence when needed
Experience with Cadence Virtuoso, ADE Explorer/Assembler, Spectre, SKILL, design libraries, CDF, techfiles, display resources, or analog/RF/mixed-signal design flows
Experience with Siemens Calibre DRC/LVS/PEX/xRC, Synopsys ICV/StarRC, Cadence Pegasus/Quantus, or related physical verification/extraction tools
Exposure to PDK installation, PDK QA, foundry design-rule manuals, rule decks, model files, LVS mapping, extraction setup, or PDK release management
Exposure to digital design and verification flows such as simulation, regressions, synthesis, STA, power analysis, formal/lint, or regression infrastructure
Familiarity with HPC environments, job schedulers such as Slurm or LSF, license servers, FlexNet, Linux modules, wrappers, NFS/storage, and shared compute systems
Ability to write clean scripts, parse logs, build sanity checks, and turn repeated errors into automated preflight checks or user-facing runbooks
Interest in AI/LLM-assisted EDA workflows, including log triage, runbook retrieval, flow diagnostics, test generation, and signoff report automation

Responsibilities

Support day-to-day EDA/CAD workflows for RFIC and silicon engineering teams, including tool launch, environment setup, PDK usage, simulation, physical verification, extraction, and related Linux workflows
Support analog/RF/mixed-signal specific flows (Virtuoso, Spectre, EM tools, etc.) in addition to digital and physical verification flows
Assist with PDK installation, qualification, version tracking, release notes, and deployment support for supported foundry processes
Triage DRC, LVS, PEX, simulation, EM, license, HPC, and environment issues using reproducible debug practices: command, log path, tool version, PDK version, run directory, expected result, actual result, and reproduce status
Maintain and improve tool launch wrappers, setup scripts, environment modules, path configuration, project templates, and onboarding material
Build lightweight automation in Python, Tcl, SKILL, shell, Perl, Makefile, or similar languages for log collection, preflight checks, license/tool health checks, regression reporting, and recurring issue reduction
Create and run targeted QA tests for PDK updates, tool upgrades, wrapper changes, vendor patches, and flow changes before broad deployment
Maintain clear runbooks and Confluence documentation for common EDA flows, including DRC/LVS/PEX debug, Cadence/Virtuoso setup, simulation setup, HPC job submission, license issues, and common user errors
Partner with design, layout, verification, physical design, IT/HPC, foundry, and EDA vendor teams to resolve blocked flows and improve methodology robustness
Identify recurring support patterns and help convert one-off fixes into durable flow changes, documentation, automation, or vendor/IT escalations
Support configuration-management and data-management workflows, such as Perforce, Cliosoft, or similar systems, as needed for silicon design teams
Contribute to modern EDA workflow improvements, including AI-assisted log triage, rule-deck validation, issue classification, signoff reporting, and designer self-service tools under senior guidance

Benefits

long-term incentives, in the form of company stock or long-term cash awards
potential discretionary bonuses
ability to purchase additional stock at a discount through an Employee Stock Purchase Plan
comprehensive medical, vision, and dental coverage
access to a 401(k) retirement plan
short and long-term disability insurance
life insurance
paid parental leave
various other discounts and perks
3 weeks of paid vacation
10 or more paid holidays per year
paid sick leave