EDA Design Flow Development Engineer

Intel•Hillsboro, CA

2d•Hybrid

About The Position

Join Intel in shaping the future of technology. As an EDA Tools Hardware Engineer, you will play a pivotal role in enabling groundbreaking innovations that power Intel's leadership in semiconductor design and manufacturing. We are seeking an experienced EDA CAD / Tool Flow Development Engineer to develop and maintain transistor-level electromigration (EM) and IR drop analysis flows for custom IPs, embedded memories, SRAMs, analog/mixed-signal interfaces, and high-performance custom macros across advanced semiconductor technologies. This role focuses on CAD methodology, automation infrastructure, power integrity analysis flows, and silicon correlation for transistor-level reliability verification. The engineer will work closely with circuit design, physical design, package, reliability, and signoff teams to enable scalable and accurate EM/IR analysis methodologies for advanced-node designs. The ideal candidate has strong expertise in transistor-level power integrity analysis, SPICE-based verification, parasitic-aware reliability modeling, and automation development using industry-standard EM/IR signoff tools.

Requirements

Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science, or a related field, and 6+ years of experience; 4+ years of experience with a Master's degree; or 2+ years of experience with a PhD.
EM/IR reliability concepts (Electromigration, and Power Drop)
Experience with Redhawk/Totem tools
Scripting and automation skills in Linux environments

Nice To Haves

CMOS circuit operation
Power delivery networks
SPICE simulation
Parasitic extraction fundamentals
Advanced-node design challenges
Transistor-level power integrity analysis flows

Responsibilities

Develop and maintain transistor-level electromigration (EM) and IR drop analysis flows for custom IPs, embedded memories, SRAMs, analog/mixed-signal interfaces, and high-performance custom macros across advanced semiconductor technologies.
Focus on CAD methodology, automation infrastructure, power integrity analysis flows, and silicon correlation for transistor-level reliability verification.
Work closely with circuit design, physical design, package, reliability, and signoff teams to enable scalable and accurate EM/IR analysis methodologies for advanced-node designs.