EDA- CAD Engineer

Western Digital•San Jose, CA

2d•Onsite

About The Position

The job opening is for a full-time Electronic Design Automation (EDA) CAD Engineer in the Design Group in Western Digital's research department. The role will be a part of a multi-functional team whose aim is to develop and eventually commercialize Western Digital's strategic radiation hardened memory technology.

Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
5+ years of experience in an EDA CAD engineering or design flow automation role.
Hands-on experience with industry-standard tools.
Strong understanding of modern semiconductor manufacturing processes and physical design rules.
Experience developing memory cell models for inclusion in simulation tool environment, such as Verilog-A
Strong proficiency in scripting languages such as Python, Tcl, Perl, or Shell scripting (bash/csh).
Strong working knowledge of Linux/Unix environments, compute grid/scheduler management (e.g., LSF, Slurm, Grid Engine), and version control systems (e.g., Git, Perforce).

Responsibilities

Design, implement, and maintain robust CAD flows and methodologies for analog and mixed-signal IC design (spanning simulation, physical design, verification and familiarity with RTL/synthesis).
Running and Debugging Physical Verification flows including DRC, LVS, ERC and Antenna Checks
Develop custom scripts and internal utilities to automate repetitive design tasks, improve tool interoperability, and maximize engineering efficiency.
Install, configure, and integrate industry-standard EDA tools (Cadence, Synopsys, Siemens/Mentor Graphics) into our infrastructure. Provide technical support to the design teams.
Monitor and optimize compute resource utilization, license usage, and disk space. Troubleshoot design flow bottlenecks, license issues, and tool crashes.
Act as the primary technical liaison with EDA tool vendors to resolve software bugs, evaluate new features, and manage license compliance.
Maintain design data management (revision control) systems and ensure clean, reproducible workspace environments
Coordination of a Split-Fab Design environment for WD PDKs (for Memory Array Layers) and a CMOS Foundry PDK (for Operational Circuitry)
Development of EDA Tool Design Rules for WD’s Memory Array Layers
Defining and executing the split-fab tape out flow

Benefits

paid vacation time
paid sick leave
medical/dental/vision insurance
life, accident and disability insurance
tax-advantaged flexible spending and health savings accounts
employee assistance program
other voluntary benefit programs such as supplemental life and AD&D, legal plan, pet insurance, critical illness, accident and hospital indemnity
tuition reimbursement
transit
the Applause Program
employee stock purchase plan
the WD Savings 401(k) Plan