DPU Performance Architect, Infrastructure Silicon

Meta•Austin, TX

23h•$178,000 - $250,000

About The Position

Meta's Infrastructure Silicon organization designs custom silicon that powers our data center infrastructure — SmartNICs/IPUs/DPUs, AI accelerators, and networking ASICs. We are seeking an experienced Performance Architect to drive performance modeling, analysis, and validation of our Data Processing Unit (DPU) architectures. In this role you will influence architecture and microarchitecture decisions from early path-finding through RTL validation and silicon correlation.

Requirements

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
8+ years of relevant industry experience in developing analytical/tool based models and performance analysis with focus on networking and storage architectures
Detailed understanding of DPU architectures: network virtualization, storage disaggregation, networking and storage protocols such as RoCE, NVMe, fabric architectures
Experience in workload analysis and characterization, and abstracting key performance features into models for analysis
Proficiency in languages for model development (e.g. Python, C/C++, SystemC)
Experience with data center workloads and benchmarking methodologies
Experience with RTL performance validation, including authoring and executing performance test plans and correlating pre-silicon performance models with post-silicon measurements
Experience driving analysis independently and influencing architectural direction through data

Nice To Haves

PhD in Computer Science, Computer Engineering or Electrical Engineering
15+ years of relevant industry experience in developing analytical/tool based models and performance analysis with focus on networking and storage architectures
Experience with hardware description languages (e.g., SystemVerilog, VHDL) and simulation environments used in ASIC development flows
Experience building or scaling performance modeling infrastructure for hyperscale data center ASICs, including network, storage, or AI inference accelerator designs
Experience with post-silicon performance validation and model-to-hardware correlation methodologies
Experience developing Python-based automation pipelines for simulation orchestration, regression testing, and performance data analysis
Experience with GPU, machine learning, multi-threaded programming paradigm
Experience with high-level synthesis, power-performance-area trade-off analysis, or PPA-driven microarchitectural optimization

Responsibilities

Analyze performance of current and future SmartNIC/IPU/DPU architectures with focus on end-to-end transaction flows, host-to-DPU offloading options, evaluation of SoC architectural options
Quantify architectural/micro-architectural trade-offs wrt PPA to inform and guide design decisions
Analyze and characterize DPU workloads to abstract key performance-relevant behaviors and incorporate into representative models and synthetic benchmarks
Develop and enhance performance models, simulation tools, and methodologies to evaluate future DPU architectures
Drive RTL performance validation, including development of comprehensive performance test plans, coverage criteria, and correlation of RTL results against architectural models
Correlate pre-silicon performance projections with post-silicon measurements and drive methodology improvements based on findings