Distinguished Engineer, ASIC (CONTRACT)

Butterfly Network•Burlington, MA

9d•Hybrid

About The Position

The role of the Distinguished Engineer, Digital ASIC Designer offers the opportunity to work within the heart of the product development team to own the core of what will set Butterfly Network apart. This individual will design, implement, and verify digital signal processing, high speed interface, and system-on-a-chip logic for a suite of next-generation products.

Requirements

BS/MS/PhD in EE/CE/CS or equivalent practical tapeout experience.
8–12+ years (typical Principal level) in digital IC / ASIC / SoC design with significant hands-on RTL ownership.
Strong understanding of digital IC implementation at the silicon level, including timing closure implications, clock/reset domain architecture, power-aware design, and PPA (power, performance, area) tradeoffs.
Proven ability to own complex digital IC subsystems from architecture and PPA tradeoffs through RTL implementation, verification signoff, and tapeout handoff to physical design.
Strong RTL skills in SystemVerilog/Verilog to implement silicon-proven digital architectures, including pipelined datapaths, control logic, state machines, and high-throughput streaming interfaces.
Experience architecting sustained high-throughput digital datapaths, including buffering, arbitration, backpressure, bandwidth budgeting, and SRAM/memory hierarchy design.
Prior work at advanced technology nodes (28nm or smaller), including timing closure challenges and integration of third-party IP.
Experience collaborating with verification teams to validate complex digital architectures and resolve functional issues through tapeout signoff.
Comfortable working cross-functionally with analog, systems, and packaging/board teams to close chip-level requirements and integration details, including hardware–firmware interfaces (register maps, control/status paths, data-plane contracts).

Nice To Haves

Experience implementing compute-intensive digital pipelines (e.g., DSP, beamforming, AI, or MAC-heavy/vector datapaths).
Exposure to medical imaging / ultrasound systems, beamforming pipelines, or sensor data acquisition architectures.
Experience designing or integrating programmable digital compute blocks (e.g., AI accelerators, MPUs, or eFPGA fabrics), including instruction/control interfaces, memory hierarchy, data movement, and PPA tradeoffs.

Responsibilities

Design, implement, and verify digital signal processing, high speed interface, and system-on-a-chip logic for a suite of next-generation products.
Own complex digital IC subsystems from architecture and PPA tradeoffs through RTL implementation, verification signoff, and tapeout handoff to physical design.
Architect sustained high-throughput digital datapaths, including buffering, arbitration, backpressure, bandwidth budgeting, and SRAM/memory hierarchy design.
Collaborate with verification teams to validate complex digital architectures and resolve functional issues through tapeout signoff.
Work cross-functionally with analog, systems, and packaging/board teams to close chip-level requirements and integration details, including hardware–firmware interfaces (register maps, control/status paths, data-plane contracts).