Director, Signal and Power Integrity Engineering

Advanced Micro Devices, Inc•San Jose, CA

8d•Onsite

About The Position

Lead a growing Signal and Power Integrity Engineering team within AMD's Adaptive and Embedded Computing Group (AECG). This role will drive SI/PI strategy and execution across package, board, and system-level designs while leading a team of engineers and supporting the development of next-generation products. Working closely with Architecture, Package Design, PCB Design, Silicon Engineering, Product Engineering, and Manufacturing teams, this leader will play a critical role in delivering successful products, advancing SI/PI methodologies, and helping scale the organization as the business continues to grow.

Requirements

A strong technical leader with deep Signal Integrity and Power Integrity expertise, excellent communication skills, and a collaborative leadership style.
Ability to develop engineering talent, influence across organizations, manage competing priorities, and effectively resolve conflicts while driving teams toward common objectives.
Self-starters who can independently lead complex technical initiatives, build high-performing teams, and consistently deliver results in a fast-paced environment.
MS or PhD in Electrical Engineering

Nice To Haves

Excellent analytical and problem-solving skills along with attention to details.
Need a self-starter, someone able to drive tasks independently and efficiently to completion.
Strong/effective communication skills.
Enthusiastic team-first mentality.
Experience with PCB, Package and IC level power delivery networks.
Experience in silicon packaging and PCB design for signal and power integrity.
Experience with high-speed digital signaling interfaces such as PCIE, GDDR6, HDMI.
Expertise in electrical modeling EDA and AMS tools such as ADS, HFSS, SIwave, HSPICE.
Expertise in electromagnetic theory and circuit analysis.
Experience with programming in Python, C++, Matlab.

Responsibilities

Managing and Planning Signal Integrity and Power Integrity development.
Planning with Collateral Teams in terms of deliverables and receivables in timely manner.
Driving system SIPI design and layout guidelines.
Coordinating with HW design team, layout team, NPI and manufacturing vendors to resolve SI/PI related issues.
End-to-end channel simulations for multi gigabit serial lines like 56Gbps, 112Gbps and beyond.
SI/PI analysis simulations of HBM/ /DDR4/LPDDR4/DDR5/LPDDR5 and other memory buses.
Characterizing the various interfaces in the product and verifying the simulations against measurements.
Preparation of and implementing checklists for various stages of PCB development.
Worked with architecture team, package design team and PCB design team for future PCB technology.