Director, Process Engineer – Dry Etch

Intel CorporationHillsboro, OR
$211,400 - $298,440Hybrid

About The Position

Intel is transforming from an Integrated Device Manufacturer (IDM) to a leading foundry service provider, offering world-class manufacturing capabilities to customers worldwide. Our Manufacturing Development and Customer Engineering (MDCE) organization is at the forefront of this transformation, focusing on yield improvement, performance optimization, and exceptional customer service delivery. We are responsible for improving process capability for Intel's technology nodes from initial product qualification to high volume manufacturing. We are seeking a Director, Process Engineer – Dry Etch to join our our team within MDCE. This role leads dry etch process engineering efforts to drive technology development, process capability, and manufacturability across advanced CMOS technologies. This role will be responsible for development, optimization, and sustaining of dry etch processes across modules that may include plasma etch, reactive ion etch (RIE), atomic layer etch (ALE), conductor etch, dielectric etch, thermal etch, and related post-etch treatment or clean processes.

Requirements

  • 10+ years of relevant work experience in the semiconductor industry with a strong focus on dry etch process development, process integration, or high-volume manufacturing support.
  • Master's degree in Electrical Engineering, Chemical Engineering, Mechanical Engineering, Materials Science, Physics, Chemistry, or a related technical field.
  • 10+ Hands-on experience with dry etch process development, plasma etch equipment, recipe optimization, process characterization, and troubleshooting.
  • 10+ Strong history of collaboration across process modules, integration teams, equipment engineering, manufacturing, yield, defect metrology, and external suppliers.
  • Ability to work in a dynamic fab environment, support urgent manufacturing issues, and drive technical closure under schedule pressure.
  • Strong understanding of dry etch process fundamentals, plasma chemistry, etch mechanisms, profile control, selectivity, microloading, CD control, chamber matching, and defect reduction.
  • Demonstrated ability to use structured problem-solving methods, data analysis, and engineering judgment to resolve complex process and equipment issues.
  • Ability to plan and execute experiments, interpret metrology and inline data, and drive timely decisions in a fast-paced manufacturing environment.
  • Ability to work effectively with Integration, Lithography, Thin Films, Cleans, Yield, Defect Metrology, Quality and Reliability, equipment engineering, and supplier teams.
  • Excellent written and verbal communication skills, with the ability to interpret and present technical information clearly to various audiences.
  • Strong self-initiative, persistence, and the ability to navigate ambiguity and drive clarity in key areas.
  • Ability to gather, analyze, and interpret data to drive results.
  • Willingness to handle high degrees of task and deadline pressure in a dynamic environment while remaining focused.
  • Strong knowledge of semiconductor process development, technology transfer, process control, fab operations, and high-volume manufacturing expectations.

Nice To Haves

  • Doctoral degree in Electrical Engineering, Chemical Engineering, Materials Science, Physics, Chemistry, or a related technical field is a plus.
  • Substantial technical background in dry etch for advanced CMOS technologies, including plasma chemistry, conductor or dielectric etch, pattern transfer, spacer etch, hard mask open, or atomic layer etch.
  • Demonstrated history of delivering process improvements in technology development, process transfer, ramp, or HVM organizations.
  • Experience with advanced logic technologies, including Gate-All-Around (GAA), advanced patterning, or highly scaled interconnect structures.
  • Experience partnering with dry etch equipment suppliers on chamber matching, hardware improvements, productivity, defectivity, and process capability.
  • Previous related work experience in a semiconductor foundry, logic technology development, or high-volume manufacturing environment is preferred.
  • Demonstrated experience using data analysis, statistical process control, design of experiments, and structured problem-solving methods to improve process performance.
  • Experience working with metrology and inspection data such as CD-SEM, profile metrology, film thickness, defect inspection, overlay, electrical test, or yield data to drive process decisions.

Responsibilities

  • Primary responsibilities will reside at the intersection of technology development and High-Volume Manufacturing (HVM), especially on new or transferred dry etch processes that require engineering to meet high volume requirements.
  • This includes driving safety, quality, performance, throughput, process capability, profile control, critical dimension uniformity, selectivity, lower defectivity, improved yield, and lower cost.
  • This role will partner successfully with internal organizations, factory teams, and external suppliers to meet Intel foundry customer needs on schedule.
  • Define and execute process experiments, analyze data, resolve tool and process issues, partner with cross-functional stakeholders, and deliver robust etch solutions that meet Intel foundry technology roadmap requirements.
  • The Dry Etch Engineer will be a strong technical contributor with expertise in plasma processing, etch equipment, process integration, metrology interpretation, and collaboration with Integration, Lithography, Thin Films, Cleans, Yield, Defect Metrology, and supplier teams to deliver modular solutions that meet technology targets.
  • This dry etch engineer will support process development, transfer, optimization, and sustaining activities that deliver significant yield improvement, performance enhancement, defect reduction, variation reduction, and cost improvement for multiple technology nodes, including advanced foundry technologies.
  • Dry Etch Process Development: Develop, optimize, and sustain dry etch processes to meet device, integration, yield, defect, performance, and manufacturability requirements.
  • Process Capability Improvement: Drive improvements in critical dimension control, profile control, uniformity, selectivity, chamber matching, defectivity, process window, throughput, and cost.
  • Data-Driven Problem Solving: Design and execute experiments, analyze process and metrology data, identify root causes, and implement corrective actions.
  • HVM Enablement: Support process transfer, ramp readiness, excursion response, tool qualification, recipe optimization, and manufacturing health improvements.
  • Cross-Functional Collaboration: Work closely with TD, HVM factories, Integration, Lithography, Thin Films, Cleans, Defect Metrology, Yield, Quality and Reliability, and supplier teams to deliver integrated process solutions.
  • Supplier Engagement: Partner with dry etch equipment suppliers to resolve hardware, process, chamber matching, and productivity issues.
  • Technical Documentation: Document process learning, experiment results, best known methods, control plans, and transfer requirements clearly and accurately.
  • Rapid Execution: Conceptualize strategies and put them into motion swiftly to meet challenging schedules.
  • Ownership and Accountability: Own assigned process areas, surface risks early, remove roadblocks, and drive issues to closure.
  • Work together, in person: Work together with team members in person to enable faster decision making and problem resolution.

Benefits

  • competitive salary
  • financial benefits such as bonuses
  • life and disability insurance
  • opportunities to buy Intel stock at a discounted rate
  • Intel stock awards
  • excellent medical plans
  • wellness programs
  • amenities
  • time off
  • recreational activities
  • discounts on various products and services
  • creative rewards
  • health
  • retirement
  • vacation
© 2026 Teal Labs, Inc
Privacy PolicyTerms of Service