Director, Physical Design

Cisco•Delta, BC

1d•$213,400 - $410,500•Remote

About The Position

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. With 2,100 employees across 16 countries, we design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's revolutionary solutions by designing, developing and testing some of the most complex ASICs being developed in the industry.

Requirements

Bachelor’s Degree in a technical field, preferably engineering and 15+ years of experience in the hardware industry with proven management experience leading SoC and Physical Design teams.
Demonstrable experience leading and managing large ASIC developments in advanced process nodes.
Prior experience in developing Physical Design execution schedules and tracking milestones.
Demonstrable hands-on experience in ASIC design from concept to release.

Nice To Haves

Knowledge of industry-standard PnR and Sign-off tools and their capabilities.
Hands-on experience in block-level synthesis, place and route, timing closure, and advanced power/integrity analysis.
Proficiency in scripting languages such as Tcl and Python.
Expertise in managing Static Timing Analysis (STA), timing closure, and design constraints.
Self-motivated with the ability to work effectively in a highly cross-functional, global team environment.

Responsibilities

Develop and manage SoC execution schedules, tracking critical milestones and communicating project status and risks to senior management.
Own the optimization of floor-plans, area, and interconnects during early chip development to meet stringent Power, Performance, and Area (PPA) goals.
Drive SoC Physical Design implementation in advanced process nodes, leading a world-class team of Physical Design, Circuit Design, DFT, and integration engineers.
Maintain close interaction with global teams across RTL, NPI, Packaging, DFT, and Architecture to identify improvement opportunities and review design constraints.
Build and oversee the development of automation utilities and infrastructure to optimize chip area, improve quality, and accelerate execution speed.
Conduct periodic design reviews with deep technical dives—including EMIR analysis and timing signoff closure—to ensure high-quality work and schedule alignment.
Build and scale a high-performing team of passionate leaders as the organization grows.
Apply an expert understanding of both Front-End (FE) and Back-End (BE) ASIC flows to drive design methodology from concept to release.

Benefits

medical, dental and vision insurance
a 401(k) plan with a Cisco matching contribution
paid parental leave
short and long-term disability coverage
basic life insurance
Cisco restricted stock units
10 paid holidays per full calendar year
1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday
paid year-end holiday shutdown
4 paid days off for personal wellness
16 days of paid vacation time per full calendar year (non-exempt)
flexible vacation time off program (exempt)
80 hours of sick time off provided on hire date and each January 1st thereafter
up to 80 hours of unused sick time carried forward from one calendar year to the next
Additional paid time away may be requested to deal with critical or emergency issues for family members
Optional 10 paid days per full calendar year to volunteer
annual bonuses (for non-sales roles)
performance-based incentive pay (for sales roles)