Director of eSoftware Engineering - FPGA / Equities Low Latency Trading

JPMorganChase • Jersey City, NJ

2d

About The Position

If you are a software engineering leader ready to take the reins and drive impact, we’ve got an opportunity just for you. As a Director of eSoftware Engineering at JPMorgan Chase within the Equities Electronic Trading team, you will set technical direction and personally contribute to the design and delivery of ultra-low latency market infrastructure used in equities electronic trading. You will build ultra-low latency pipelines spanning market data ingest, processing, and distribution as well as trading and execution workflows, with rigorous verification and production-grade operational controls. This role requires deep networking expertise (including TCP/IP), experience with Layer 1 switching and low-latency connectivity (including microwave), and the ability to take large programs from requirements through delivery, coordinating with internal compute and networking service organizations and managing outside vendors. This is a technical leadership role; will guide the team through architecture, design reviews, and execution. A core priority of this role is to advance the team's adoption of AI-assisted and spec-driven FPGA development and verification workflows, including executable specifications, automated review, and traceability from spec to silicon, with examples such as AI-assisted RTL and testbench generation to improve quality, throughput, and time-to-market.

Requirements

• Formal training or certification on software engineering concepts and 10+ years applied experience.
• In addition, 5+ years of experience leading technologists to manage, anticipate and solve complex technical items within your domain of expertise and more broadly across the organization
• Strong expertise and hands-on FPGA development experience in low-latency electronic trading and HFT systems.
• Demonstrated expertise building ultra-low latency FPGA pipelines , including end-to-end performance measurement, deterministic design techniques, and latency/throughput trade-offs.
• Advanced verification capability using Python and Cocotb , including functional coverage, constrained/random strategies as appropriate, regression automation, and debug discipline; familiarity with SystemVerilog and UVM as complementary verification approaches.
• Strong market data domain knowledge across ingest, processing, and distribution in production trading environments.
• Deep understanding of networking with proven implementation and troubleshooting experience in TCP , and strong competence across UDP, IP, multicast, ARP, and PTP , including packet parsing, buffering, congestion/flow considerations, and timestamping.
• Experience with Layer 1 switching and ultra-low latency signal distribution concepts, including deterministic path design and the physical and topology constraints typical of low-latency market access environments.
• Hands-on experience with microwave / wireless low-latency connectivity for market access, including latency budgeting, availability and environmental considerations, link engineering trade-offs, integration with FPGA-based termination/processing, and direct collaboration with specialist vendors and carriers.

Nice To Haves

• Expertise with leading FPGA vendor toolchains and devices, including high-speed transceivers and high-speed Ethernet MAC/PCS integration.
• Host/FPGA integration experience, including PCIe , DMA , AXI , driver/firmware interfaces, and performance profiling across the full stack.
• Familiarity with exchange connectivity protocols, including production considerations for resiliency and change management.
• Experience with, or strong interest in, AI-assisted and spec-driven approaches to FPGA development and verification, including executable specifications, AI-assisted RTL generation and refactoring, testbench and stimulus generation, automated code review, bug triage, and performance tuning, applied with appropriate guardrails for correctness, IP protection, confidentiality, and reproducibility.
• The successful candidate will help build and scale this capability within the team over time; deep prior expertise is not required at hire.

Responsibilities

• Architect, implement, and optimize ultra-low latency FPGA-based pipelines for market data ingest, processing, and distribution as well as trading workflows, with a focus on determinism, measurement discipline, and production readiness.
• Design and deliver high-performance network subsystems on FPGA, including deep TCP/IP expertise and complementary protocol support (UDP, IP, multicast, ARP), time synchronization (PTP), and loss/latency instrumentation suitable for production operations.
• Engineer and integrate Layer 1 switching and ultra-low latency signal distribution capabilities, including deterministic path design and the physical and topology constraints typical of low-latency market access environments.
• Partner with network engineering teams and external vendors to design, validate, and operate low-latency connectivity solutions, including microwave / wireless links, with clear operational runbooks and measurable service-level objectives.
• Own verification strategy and execution, building robust testbenches in Python/Cocotb to achieve high functional coverage, strong regression quality, and fast debug cycles.
• Drive timing closure and performance predictability, including floorplanning, static timing analysis, CDC/RDC correctness, power optimization, and post-route validation under realistic traffic and corner conditions.
• Serve as technical lead for a team hardware and software engineers across the program lifecycle, taking large programs from requirements through production rollout while coordinating with internal compute and networking service organizations and managing outside vendors.
• Lead the team's adoption and scaling of AI-assisted and spec-driven workflows for FPGA development and verification, including executable specifications, spec-to-implementation traceability, AI-assisted RTL generation and refactoring, automated code review, testbench and stimulus generation, bug triage, and performance tuning, with appropriate controls for correctness, IP protection, confidentiality, and auditability.

What This Job Offers

• Job Type: Full-time
• Career Level: Director
• Education Level: No Education Listed