Director of 3D Stacked Logic Design

SK hynix America•San Jose, CA

8d•$250,000 - $300,000•Onsite

About The Position

SK hynix America is at the forefront of semiconductor innovation, developing advanced memory solutions for AI data centers and mobile technology. As a global leader in HBM, DRAM, and NAND flash, we are making significant investments in the U.S. and are committed to sustainable operations. We are seeking innovative minds to join our collaborative team, pioneer next-generation memory technologies, expand our market footprint, and define the future of computing.

Requirements

Bachelor’s degree or higher in Electrical Engineering or a related discipline.
Development of Digital Logic IP/SoC based on Hardware Description Languages (Verilog, VHDL).
8+ years of relevant experience in the following areas:
Experience in RTL design and implementation memory PHY, hard macro IP for high-speed circuit, or high-speed digital IP design
Experience in memory controller
Experience in memory Built-in Self Test(BIST), DRAM Design for Test(DFT) / Design for Debug(DFD)
Deep understanding of PPA analysis and optimization, and physical design.
Excellent verbal and written communication in English; ability to present technical concepts to cross functional teams and senior management.

Responsibilities

Lead the design of high-speed digital IP for 3D-stacked DRAM peripheral circuits and DFT with U.S.-based customers (including RTL design to implementation).
Drive foundry Verification of Service-Ready IPs and Infrastructure Setup for IP Business.
Deliver Services to Ensure Seamless IP Integration in Customer Design Environments.
Strengthen Leadership in the DRAM-on-Logic Era through advanced digital IP design for 3D-Stacked DRAM.
Provide digital IP services for 3D-stacked DRAM to enable DRAM-on-Logic system configurations for customers.
Co-design of 3D-stacked DRAM Logic Die with U.S –based customers.
Improve competitiveness through close engagement with customers in US.