Director High Speed IO Architecture & Design

Advanced Micro Devices, Inc•Santa Clara, CA

11d

About The Position

Lead AMD’s hardware/digital IP design engineering team in collaboration with internal teams and partners to develop next-generation high-speed I/O technologies. This role provides technical and managerial leadership for system, digital hardware, and front-end/RTL/logic design teams; scales the organization to develop reusable IP across a multi-product roadmap; and guides architecture, microarchitecture, and implementation within system, power, performance, and area constraints. The Director represents the digital design organization in architecture reviews and technical engagements, coordinates execution across engineering disciplines and geographies, and develops team members through mentoring and coaching. The role oversees planning, staffing, schedules, priorities, performance, and program risks; establishes design-flow practices and quality standards; and partners with physical-design and DFX teams on complete RTL-to-GDSII designs. The position also co-leads silicon-success methodology and post-silicon planning and execution, including bring-up, platform validation, characterization, parameter optimization, and productization. It supports IP production, bench-level test and validation planning, and post-silicon work through new product introduction. The role is located in Santa Clara, California and is not eligible for visa sponsorship.

Requirements

Progressive experience in digital I/O subsystem IP hardware design and technical leadership.
Strong engineering and people-management experience, including building, developing, mentoring, and leading distributed engineering or technical teams.
Demonstrated success delivering complex digital-on-top I/O subsystem IPs, including mixed-signal IPs, through high-volume production and production tape-outs in advanced FinFET CMOS nodes.
Expertise developing low-power, low-latency, high-performance I/O datapath microarchitecture between hosts and peripherals.
Demonstrated ability to concurrently manage complex IPs across multiple SoC programs.
Deep knowledge and technical experience in high-speed I/O (HSIO) and PHY digital subsystems, from architecture through implementation.
Strong knowledge of digital design methodologies, including clock-domain-crossing checks, reset checks, low-power design, synthesis, static timing analysis, and timing closure.
Experience collaborating with physical-design and functional-verification teams to deliver complete RTL-to-GDSII designs.
Strong analytical, problem-solving, decision-making, and organizational skills, including the ability to resolve complex technical and organizational challenges independently.
Excellent written and verbal communication skills, including summarizing complex issues for executives and engaging in technical discussions with architects and engineers.
Ability to manage, build, and develop high-performing, diverse technical teams through mentoring, coaching, and performance management.
Ability to establish durable working relationships and networks across functions and geographies.
Highly self-motivated, detail-oriented, results-driven, and committed to disciplined engineering practices.
Collaborative team player who develops personal leadership capability and supports the growth of others.
Master’s degree or Ph.D. in Electrical Engineering or Computer Engineering, with emphasis on I/O subsystem digital/hardware architecture and design and detailed knowledge of high-speed I/O subsystems, high-speed interconnects, and I/O subsystem/platform firmware.

Nice To Haves

Experience with high-speed I/O subsystems (SerDes/Chip-to-Chip), high-speed interconnects, and I/O subsystem/platform firmware.
Embedded firmware development experience.

Responsibilities

Provide technical leadership and direction for the hardware/digital semiconductor design engineering organization.
Lead and manage system, digital hardware, and front-end/RTL/logic designers.
Manage and scale the design team to develop reusable IP supporting a multi-product roadmap.
Collaborate with IP, sub-system, and SoC architects to translate high-level requirements into microarchitecture and design implementation plans.
Contribute to IP architecture and microarchitecture, circuit architecture, and digital subsystem blocks.
Drive architectural decisions for next-generation products within system-architecture and power, performance, and area budgets.
Represent the digital design organization in cross-functional architecture reviews, customer technical engagements, and foundry and EDA partner discussions.
Mentor front-end digital designers and microarchitects through design reviews, technical coaching, and silicon debug.
Own high-level design planning, work breakdown, task assignment, progress tracking, schedule and priority management, performance reviews, talent development, and hiring.
Partner with peer engineering directors, program managers, architects, circuit and AMS teams, and physical-design leads to deliver quality results on schedule and against technical requirements.
Proactively manage critical paths, dependencies, priorities, and overall program risk.
Collaborate across analog design, custom digital design, AMS circuit architecture, AMS design verification, functional verification, physical design, and DFX teams across multiple geographies.
Ensure cross-team alignment, engagement, and execution from architecture through production.
Co-lead silicon-success methodology, establishing first-silicon-success expectations, disciplined debug practices, and a path from characterization to production.
Define and improve front-end development flows to increase execution efficiency, effectiveness, and quality.
Establish and enforce design-flow best practices and quality standards for performance, power, reliability, area, and timing requirements.
Work with physical-design and DFX teams to deliver complete RTL-to-GDSII designs.
Co-own post-silicon planning and execution, including initial bring-up, platform validation, characterization, parameter optimization, and final productization.
Contribute to IP production and bench-level test, characterization, and validation plans with post-silicon characterization and validation teams.
Enable and support post-silicon workstreams through new product introduction.