Director, Engineering SOC/ASIC Design
Qualcomm•San Diego, CA
•$216,400 - $324,600
About The Position
Qualcomm's Cloud Business Unit is building next-generation AI inference rack scale solutions, anchored by the AI200/AI250 accelerator family. We are seeking a seasoned and experienced ASIC/Chip designer to work on the next generation AI products in the datacenter. We are looking for an experienced ASIC Lead whose expertise spans chip development process from early architecture phase to post-silicon commercialization. This role requires working in leading technology nodes and processes to innovate and deliver next-generation products.
Requirements
- Bachelor's degree in Science, Engineering, or related field and 8+ years of ASIC design, verification, validation, integration, or related work experience.
- Master's degree in Science, Engineering, or related field and 7+ years of ASIC design, verification, validation, integration, or related work experience.
- PhD in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
Nice To Haves
- Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science.
- 12+ years of ASIC design, verification, validation, integration, or related work experience.
- 4+ years of experience with architecture and design tools.
- 4+ years of experience with scripting tools and programming languages.
- 4+ years of experience with design verification methods.
- 2+ years of work experience in a role requiring interaction with senior leadership (e.g., Vice President level and above).
- 1+ year of working with operating budgets and/or project financials.
Responsibilities
- Develop architecture and module specifications
- Analyze performance, area, power, and system cost tradeoffs for different implementations
- Provide guidance to different IP teams regarding product requirements
- Work with SOC team in defining the execution plan encompassing design, DV, synthesis, DFT, PD phases leading to tapeout
- Work with Packaging team to develop System-In-Package (SIP) encompassing SOC and different memory/compute chips
- Define and monitor pre-Silicon functional and performance validation plans followed by same on Silicon
- Coordinate with Production Test Engineering to drive commercialization rollout
- Work with datacenter SW and HW teams for deployment in the datacenter.
Benefits
- competitive annual discretionary bonus program
- opportunity for annual RSU grants
- highly competitive benefits package
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What This Job Offers
Job Type
Full-time
Career Level
Director
