Digital Physical Design (P&R) Intern
NXP Semiconductors•Chandler, AZ
•Onsite
About The Position
As a Physical Design Intern, you will join a highly experienced team. Your key responsibilities will be to understand the existing flow, tools, and scripts to perform the Digital backend flow from Synthesis to GDS2 using Cadence tools. You will support multiple parallel runs to experiment with different RTL implementations and/or tool options to find the most area-optimal solution. Additionally, you will deeply study the Cadence tools’ user-manuals and user-forum discussions, and suggest improvements to existing flows and scripts that could enhance the quality and efficiency of the backend flow.
Requirements
- Pursuing Master's degree (MSEE) with majority of courses relevant to Digital Design, RTL, Digital backend flow
- Willing to relocate to Phoenix Metro area (Arizona) for the full duration of internship, and minimum 3 days per week full-day presence in NXP's Chandler office
- Excellent on problem-solving, teamwork, planning, organizing, attention to detail and communication skills
Nice To Haves
- Any prior experience with this flow is a strong plus
Responsibilities
- Understand the existing flow, tools and scripts to do Digital backend flow from Synthesis to GDS2 using Cadence tools
- Support with multiple parallel runs to experiment with different RTL implementations, and/or tools options to find the most area-optimal solution
- Deeply study the Cadence tools’ user-manuals and user-forum discussions, and suggest improvements to existing flows and scripts that could improve the quality and efficiency of the backend flow
Benefits
- online and offline learning opportunities
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What This Job Offers
Career Level
Intern
