Digital IC Design Manager

Snap•Vancouver, WA

20h•Hybrid

About The Position

Snap Inc is a technology company. We believe the camera presents the greatest opportunity to improve the way people live and communicate. Snap contributes to human progress by empowering people to express themselves, live in the moment, learn about the world, and have fun together. The Company operates Snapchat , a visual messaging app that enhances your relationships with friends, family, and the world, and Specs Inc. , a wholly-owned subsidiary dedicated to making computing more human, in addition to Bitmoji , Saturn, and other digital services. The MicroDisplay Electronics and Software team develops state-of-the-art microdisplays for use in Specs. What you’ll do: Work as part of a multi-disciplinary team designing display ICs for AR Work closely with chip architect, verification, analog design, and test functions to design a Big-D,Big-A type ASIC Manage a small team of digital designers and physical design engineers to create RTL code and its physical implementation Execute and Continuously Improve RTL design and RTL-to-gds Digital Implementation flows for our Display ICs Perform or manage RTL-based logic design, Design-for-Test, chip floorplanning, place-and-route, timing closure, physical verification, synthesis, DFT insertion, LEC Specify and configure tools and create automation Hire and manage additional new staff This position may initially include individual contributor work, until the group expands further

Requirements

BSEE or MSEE
10+ years in directly applicable work performing physical design / digital implementation
Minimum of 3 years experience in a management role
People management skills and knowledge of typical HR policies and procedures, including performance management, hiring, firing, and promotion
Strong working knowledge of logic design and RTL coding and associated functions (lint, CDC, LEC, DFT)
Strong working knowledge of digital implementation (physical design)
Strong working knowledge of integration of external and internal design IP, including analog blocks
Strong working knowledge of Cadence Innovus, Tempus, Genus and PVS tools or equivalents
Strong working knowledge of Mentor/Siemens Calibre tool suite
Scripting and automation, such as TCL, SKILL, Perl, Python and Shell scripts

Nice To Haves

Optional – see preferred Qualifications
Knowledge of Analog, Mixed-signal circuit design and custom layout
Knowledge of Siemens QuestaSim (formerly Modelsim)
Knowledge of emulation, and the Siemens Veloce Emulator
Knowledge of Cadence Innovus, Genus, Tempus tools
Knowledge of Tessent DFT tools
Knowledge of Conformal LEC tool or equivalent
Knowledge of Virtuoso custom layout tool or equivalent

Responsibilities

Work as part of a multi-disciplinary team designing display ICs for AR
Work closely with chip architect, verification, analog design, and test functions to design a Big-D,Big-A type ASIC
Manage a small team of digital designers and physical design engineers to create RTL code and its physical implementation
Execute and Continuously Improve RTL design and RTL-to-gds Digital Implementation flows for our Display ICs
Perform or manage RTL-based logic design, Design-for-Test, chip floorplanning, place-and-route, timing closure, physical verification, synthesis, DFT insertion, LEC
Specify and configure tools and create automation
Hire and manage additional new staff