Digital Hardware Engineer

Integration Innovation, Inc.•Washington, DC

12h•$115,000 - $189,000

About The Position

i3 has an exciting opportunity for a Digital Hardware Engineer to support the Naval Research Laboratory, Tactical Electronic Warfare Division. The TEWD's mission is to protect the warfighter from emerging threats by advancing electronic warfare (EW) through analysis and RDT&E of current and future technologies. Pay Range $115,000 - 189,000 The pay range for this position is a general guideline only and not a guarantee of compensation or salary. Additional factors considered in extending an offer include (but are not limited to) responsibilities of job, education, experience, knowledge, skills, and abilities, as well as internal equity, alignment with market data, geographic location, and any applicable laws.

Requirements

Bachelor’s degree in electrical/computer engineering, physics, or related field.
Minimum five (5) years of experience.
Thorough understanding of HDL (VHDL or Verilog).
Experience with buses such as RS232, RS422, UART, SPI, I2C.
Ability to generate architectural block diagrams from existing firmware designs.
Experience developing and testing FPGAs or ASICs.
Knowledge of Altera and Xilinx development environments (e.g. Vivado, Quartus, Synplify).
Knowledge of FPGA/ASIC simulation and validation environment (e.g. ModelSim, Verdi).
General knowledge of DSP coding and communication protocols.
Current TS/SCI clearance.
U.S. Citizenship required.

Nice To Haves

Master’s degree in electrical/computer engineering, physics, or related field.
Knowledge of microprocessor architecture and high speed interfaces as applied to FPGA Core functions.
Experience with analysis of existing digital logic designs.
Ability to design/recognize control flow computational paths and DSP data path components (e.g. digital filters, FFTs, and error-correction codes).
Experience authoring technical reports and presentations.

Responsibilities

Design, implement, analyze and test FPGA-based digital systems.
Develop HDL and block designs for FPGAs.
Integrate manufacturer IP FPGA cores (processor, ADC, DAC, etc.) into customized firmware architectures.
Design and validate testbench routines for simulation of FPGA designs and sub-designs.
Generate technical reports documenting design and analysis.