Remote | Digital Hardware Design & Verification Specialist — $65–$95/hour

24-Mag•New York, NY

16h•Remote

About The Position

We are sharing a specialised part-time consulting opportunity for digital hardware professionals experienced in ASIC and SoC engineering, RTL development, functional verification, hardware debugging, testbench architecture, and production silicon workflows. This role supports a remote collaboration focused on improving how advanced AI systems understand and evaluate real-world semiconductor engineering work. Selected professionals will apply their practical hardware expertise to develop realistic chip design and verification problems, create rigorous reference solutions, assess technical outputs, identify subtle engineering failures, and contribute to high-quality evaluation workflows.

Requirements

Hands-on experience in ASIC or SoC design, functional verification, formal verification, or related semiconductor engineering work
Practical exposure to production silicon, tapeout, IP integration, bring-up, or coverage closure
Strong fluency in SystemVerilog or Verilog
Experience building, reviewing, or debugging RTL and verification environments
Solid understanding of subsystem and SoC-level engineering concerns
Strong written communication and the ability to explain complex hardware decisions clearly
Availability to contribute approximately 20–40 hours per week depending on project scope
Current location in the United States
A degree in electrical engineering, computer engineering, computer science, physics, or a related technical field is helpful
Current doctoral study, graduate-level research, or professional semiconductor engineering experience is highly relevant
New graduates with strong practical project experience and senior engineers with production silicon backgrounds are encouraged to apply
Equivalent hands-on experience in chip design, verification, FPGA development, or hardware systems engineering is also highly valuable

Nice To Haves

Experience with RTL design, microarchitecture, IP integration, or subsystem development
Familiarity with NoC, PCIe, DDR, ARM, AXI, handshaking, backpressure, and clock-domain crossing
Experience with UVM, SVA, CocoTB, formal verification, coverage closure, or testbench architecture
Familiarity with Synopsys VCS, Cadence Xcelium, Siemens Questa, VC Formal, Verdi, or comparable industry tools
Experience with Icarus Verilog, Verilator, Yosys, OpenROAD, or other open-source hardware toolchains
Knowledge of PPA optimization, timing closure, synthesis, or analog and mixed-signal design verification
Previous experience with AI evaluation, technical benchmarking, or structured model assessment

Responsibilities

Design realistic chip engineering problems based on practical ASIC, SoC, RTL, debugging, or verification experience
Develop tasks reflecting production-level engineering scenarios rather than textbook exercises
Create problems involving subsystem behavior, interface protocols, multi-module dataflow, timing, coverage, and system configuration
Calibrate technical difficulty and expected outcomes against real hardware engineering standards
Develop reference RTL, testbenches, assertions, and supporting technical materials
Work with SystemVerilog, Verilog, and relevant verification methodologies
Produce clear solution paths covering design intent, implementation decisions, and expected behavior
Review technical artifacts for correctness, completeness, readability, and engineering rigor
Evaluate technical outputs across design, verification, debugging, formal analysis, and implementation workflows
Identify incorrect assumptions, protocol violations, timing issues, coverage gaps, and RTL defects
Assess whether proposed solutions reflect practical semiconductor engineering judgment
Explain technical failures clearly and document how an experienced engineer would improve the approach
Collaborate with other hardware professionals to maintain consistent standards of rigor and difficulty
Review peer-created problems, reference solutions, testbenches, and evaluation criteria
Apply structured assessment frameworks across different hardware engineering domains
Communicate technical findings clearly while working independently in a remote environment