DFx Methodology Architect
About The Position
AECG organization at AMD is looking for an experienced DFx Architecture, Methodology and Logic Design Expert with strengths in RTL and Timing to support FPGA-SoCs and custom ASICs. In this role, you will own and drive DFx Architecture definition, RTL implementation and methodology development. You have had significant success driving Architecture, Design Methodologies, RTL, and Timing to tape out and production. You are meticulous about Power, Performance and Area while driving schedule and managing cost. This role will stretch you as you lead design teams in new directions, network with our world-class, patent-holding think-tank, and negotiate amongst design, verification, validation, CAD and product engineering teams. You have excellent communication, presentation and problem-solving skills. The candidate should be comfortable working hands-on. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you.
Requirements
- Bachelors or Masters or PhD degree in computer engineering/Electrical Engineering
- Proficient with Siemens Tessent DFT flows, such as Tessent Shell, Tessent Scan, Tessent ATPG, Tessent MemoryBist, IJTAG and SSN
- Understanding of 1149.1 / 1687 standards, understanding of ATPG, experience in 2.5D and 3D IC testing
- Strong understanding of DFT Architecture and Debug methodologies
- Strong foundation in logic design, switching theory and timing
- Experience with supporting silicon debug and diagnosis
- Skilled at collaborating with teams across different geographies
- Scripting language experience: Perl, Python and TCL
Nice To Haves
- Exposure to leadership or mentorship is an asset
Responsibilities
- Define and lead SoC-DFx Architecture, Specifications and development of DFx-IPs
- Own DFx Architecture documentation, accounting for interactions with other features, the hardware and the firmware
- Implement DFx features in RTL using Verilog/SystemVerilog
- Co-owning Timing and Design Quality Checks (and waivers) for the DFx-IPs
- Work cross functionally with DFx execution and verification teams to enable integration and validation of DFx-IPs in all phases of design implementation flow
- Work closely with Design teams for Verification Test plan reviews, Timing targets and Performance/Power Verification sign offs
- Engage with validation and product teams on test plan, coverage, Silicon bring up and silicon debug
- Contribute to front-end, DFx and timing methodologies
- Drive innovation in a rapidly changing technological environment
Benefits
- AMD benefits at a glance
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What This Job Offers
Job Type
Full-time
Career Level
Senior
