DFT Manager

Marvell Technology • Ottawa, ON

86d

About The Position

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. This is an existing vacancy. Your Team, Your Impact The DFT Manager is responsible for leading the definition, implementation, and execution of Design for Test (DFT) strategies across complex silicon designs. This role ensures high test coverage, manufacturability, and product quality while balancing cost, schedule, and performance constraints. The DFT Manager leads a team of DFT engineers and works cross‑functionally with design, verification, manufacturing, product engineering, and external partners. What You Can Expect Own and define the overall DFT architecture and methodology for SoCs, ASICs, or IP blocks across multiple programs. Develop and maintain DFT best practices, automation flows, and documentation. Lead the planning, insertion, and validation of DFT features such as: Scan (full scan, compression, EDT) ATPG and fault modeling (stuck‑at, transition, cell‑aware, path delay) BIST (logic BIST, memory BIST) Boundary scan (IEEE 1149.x), IJTAG, and DFT for IOs and analog blocks Ensure high test coverage while minimizing area, power, and timing impact. Drive testability requirements from early architecture through tape‑out. Review and sign off on DFT readiness at key milestones (RTL freeze, netlist, tape‑out). Collaborate with: Design and physical teams to resolve DFT timing, congestion, and implementation issues Product engineering and manufacturing to support silicon bring‑up, yield learning, and volume production ATE and test program teams for test pattern delivery and deployment Manage and mentor a team of DFT engineers, including: Technical direction and design reviews Performance management and career development Interface with EDA vendors on tool usage, flows, and feature requirements. What We're Looking For Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field 8+ years of hands‑on DFT experience with increasing technical or leadership responsibility Strong expertise in: Scan architecture and ATPG methodologies Memory and logic BIST Fault coverage analysis and debug DFT insertion and verification flows Solid understanding of: Digital design and verification Timing, power, and physical design interactions Silicon manufacturing and test processes Proficiency with Tessent EDA tools Experience taking multiple designs from concept through successful production.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
• 8+ years of hands‑on DFT experience with increasing technical or leadership responsibility
• Strong expertise in: Scan architecture and ATPG methodologies Memory and logic BIST Fault coverage analysis and debug DFT insertion and verification flows
• Solid understanding of: Digital design and verification Timing, power, and physical design interactions Silicon manufacturing and test processes
• Proficiency with Tessent EDA tools
• Experience taking multiple designs from concept through successful production.

Nice To Haves

• Previous people management or technical leadership experience
• Strong scripting skills (e.g., Tcl, Python) for automation
• Experience with advanced nodes and low‑power designs
• Exposure to heterogeneous designs (multi‑die, chiplets, or mixed‑signal SoCs)
• Excellent communication skills and ability to influence cross‑functional teams

Responsibilities

• Own and define the overall DFT architecture and methodology for SoCs, ASICs, or IP blocks across multiple programs.
• Develop and maintain DFT best practices, automation flows, and documentation.
• Lead the planning, insertion, and validation of DFT features such as: Scan (full scan, compression, EDT) ATPG and fault modeling (stuck‑at, transition, cell‑aware, path delay) BIST (logic BIST, memory BIST) Boundary scan (IEEE 1149.x), IJTAG, and DFT for IOs and analog blocks
• Ensure high test coverage while minimizing area, power, and timing impact.
• Drive testability requirements from early architecture through tape‑out.
• Review and sign off on DFT readiness at key milestones (RTL freeze, netlist, tape‑out).
• Collaborate with: Design and physical teams to resolve DFT timing, congestion, and implementation issues Product engineering and manufacturing to support silicon bring‑up, yield learning, and volume production ATE and test program teams for test pattern delivery and deployment
• Manage and mentor a team of DFT engineers, including: Technical direction and design reviews Performance management and career development
• Interface with EDA vendors on tool usage, flows, and feature requirements.

What This Job Offers

• Job Type: Full-time
• Career Level: Manager
• Number of Employees: 1,001-5,000 employees