Device Integration Engineer

Samsung Electronics•Taylor, TX

1d•Onsite

About The Position

Samsung Austin Semiconductor is seeking a highly experienced Device Engineer to join their 2nm Gate-All-Around (GAA) device engineering team. This individual-contributor role focuses on process-device co-optimization to enhance transistor performance, targeting, reliability, yield learning, and manufacturability of GAA technology derivatives. The position requires close collaboration with integration, process module, Fab engineering, and DFM teams to deliver industry-leading device performance at the 2nm node and beyond. The role involves tackling problems of diverse scope and advanced assignments requiring considerable judgment and initiative, with minimal supervision unless major decisions are made.

Requirements

Bachelors of Science or Engineering (Electrical, Computer, Chemical, Material Science, or related areas) required.
3-8 years of relevant experience.
5+ years of industry experience is preferred.
Understanding of the interactions between process and Electrical test.
Knowledge of process flow - Familiarity with unit processes including thin films deposition, etch, diffusion, wet process, CMP, lithography, implant, anneal, etc.
Willing to work and learn in a fast-paced environment.
Analysis skills, including electrical device characterization, yield analysis, data mining, DOE, and SPC.
Must have excellent communication, documentation and presentation skills.
Must be capable of shifting focus and changing priorities - dealing with ambiguity.
Demonstrated ability to meet deadlines and commitments while managing multiple priorities.
Ability to complete assigned tasks without direct supervision.
Ability to exercise independent judgment and make decisions.
Ability to work effectively and efficiently in high stress and conflict situations.
Good communication and interpersonal skills.

Nice To Haves

Masters or PhD is a plus.
SPICE modeling and simulation experience preferred.
Spotfire experience highly preferred.
Ability to reason logically and make sound decisions, to consider alternative and diverse perspectives, to communicate effectively both orally and in writing, to remain poised under all circumstances, and to interact effectively with people in a positive manner that engenders confidence and trust.

Responsibilities

Perform split lot design and DOE analysis to identify key process knobs impacting device performance and yield.
Collaborate with integration and module teams to resolve device-process interactions and define optimization paths.
Lead root cause analysis for device failures and non-conformances; drive corrective actions across fab operations.
Drive Task Force Teams to solve systematic yield, performance, or reliability issues.
Ensure targeting of transistor focused Electrical Test (ET) trends to Customer/Product specifications and perform timely root cause study to shifts or abnormality.
Analyze process interactions (inline metrology, FDC, etc.) to ET while also understanding ET data effect on Parametric Yield.
Own Parametric Yield and Wafer Acceptance Electrical Test (WAT) management for one or more Customer Accounts/Products.
Support unit process (ex: CMP, Etch, etc) or process integration team with evaluation of device impact for key change points (ex: for performance/ yield improvement activities, etc.).
Generate written reports and oral presentations for internal management, external teams, and company executives.
Conduct Local Layout Effects (LLE) analysis to characterize and mitigate transistor performance variability driven by neighboring pattern density, in GAA nanosheet devices, and providing paths to module and fab engineering to improve process and feeding findings into design rule definition and SPICE models, where applicable.
Lead Material to Hardware Correlation (MHC) task force to systematically link upstream material and process metrology data (film composition, stress, defectivity) to final electrical device performance, enabling predictive process control and accelerating yield ramp at the 2nm node.