Device Engineer

Samsung Electronics•Taylor, TX

23h•$106,000 - $174,500•Onsite

About The Position

The Yield Analysis & Improvement role is a critical technical leadership position focused on maximizing semiconductor manufacturing efficiency and product quality. The primary objective is to own end-to-end yield performance across wafer sort, parametric, and final testing. By leveraging advanced data mining, statistical analysis, and machine learning, the role identifies key yield limiters and develops automated analytics pipelines to correlate electrical failures with inline defect data, ensuring a seamless transition from technology launch to mass production ramp. Beyond data analysis, this role serves as a central hub for cross-functional collaboration. The engineer partners with Process Integration, Module, and Design teams to optimize process windows, reduce variability, and resolve layout-dependent issues. Utilizing structured problem-solving methodologies and partnering with Failure Analysis (FA) teams for physical and electrical correlation, the role drives the root cause investigation and corrective actions necessary to contain yield excursions and improve overall manufacturability. At the staff level, the role expands into strategic yield management and organizational leadership. This involves defining the long-term yield roadmap, establishing key performance indicators (KPIs), and leading high-priority task forces to resolve critical production risks. Furthermore, the position is responsible for mentoring junior engineers and interfacing with executive leadership to provide transparent insights into the health and risks of the fabrication process.

Requirements

B.E. M.Sc., or PhD in Electrical Engineering, Materials Science, Physics, Applied Physics, or related field.
5+ years of experience in semiconductor yield or process integration preferred
Foundry Background: Direct experience at a leading-edge fab focusing on FinFET or Gate-All-Around (GAA) architectures.
Strong understanding of semiconductor device physics, wafer fabrication, and transistor performance and semiconductor process (Lithography, Etch, CMP, PVD/CVD).
Coding skills for data manipulation (Python, SQL).
Proficiency in statistical analysis software (Spotifre, JMP, Related python library).

Responsibilities

Own end-to-end yield performance across wafer sort, parametric test, and final test.
Perform advanced data mining and statistical analysis to identify yield limiters and drive improvement actions.
Generate yield detractors and correlate yield to electrical, inline, and defect data.
Collaborate with process integration and module teams to reduce variability and improve process windows.
Define and execute defect reduction strategies. Partner with Module and Process Integration engineers to solve complex critical defect issues.
Support technology launch, ramp, and transfer across nodes and fab.
Lead root cause investigations using structured problem-solving methodologies.
Partner with FA teams (EFA/PFA) to correlate physical defects with electrical signatures.
Collaborate with Design and Product teams to ensure manufacturability and resolve layout-dependent yield issues before mass production ramp.
Drive containment and corrective actions for yield excursions.
Apply statistical analysis, machine learning, and predictive modeling to yield datasets.
Develop automated analytics pipelines (Python, JMP, SQL).
Develop and maintain sophisticated yield models.
Define yield roadmap, KPIs, and improvement strategy.
Lead task forces for major yield excursions.
Mentor junior engineers and establish best practices.
Interface with executive leadership on yield health and risks.