Design Verification Lead, AI Hardware

Tenstorrent•Toronto, ON

1d•$100,000 - $500,000•Hybrid

About The Position

Tenstorrent is seeking a Verification Lead for their next-generation AI hardware. This role involves guiding a team of Verification Engineers, developing test strategies to validate the functionality and performance of AI cores. The position requires expertise in AI-specific data types, common AI data-movement compute patterns, and on-chip network validation, along with strong leadership and collaboration skills. This is a hybrid role based in Toronto, ON. The company welcomes candidates at various experience levels, and the final level and offer will be determined during the interview process.

Requirements

Proven track record of leading teams through complex tape-outs.
Expertise in high-performance compute, specifically focused on AI/ML architectures and tensor-based operations.
View verification through a system-level lens, ensuring hardware, software, and on-chip networks (NoC) harmonize.
Proficient in UVM, SystemVerilog, and cocotb.
Expertise in architecting verification plans for mixed-precision data types (FP8, BF16, INT8).
Expertise in validating the accuracy of complex AI transformations.
Deep experience benchmarking on-chip networks under high-demand traffic.
Experience ensuring throughput, bandwidth, and congestion management meet peak requirements.
Proactive approach to system stability.
Experience implementing robust concurrency controls and multi-core synchronization.
Ability to develop portable test strategies that scale seamlessly from subsystem-level simulations to FPGA and final Silicon.
Collaborative mindset that bridges the gap between hardware architecture and software requirements.

Nice To Haves

AI-specific data types
Common AI data-movement compute patterns
On-chip network validation
Elevating team capabilities and driving rigorous coverage-driven methodologies.
Evolving workload dynamics and how they stress memory access patterns uniquely within your architecture.
Project-specific performance bottlenecks.

Responsibilities

Guide a top-tier team of Verification Engineers.
Shape test strategies to validate functionality and performance of our AI core.
Architect verification plans for mixed-precision data types (FP8, BF16, INT8) and validate the accuracy of complex AI transformations.
Benchmark on-chip networks under high-demand traffic, ensuring throughput, bandwidth, and congestion management meet peak requirements.
Implement robust concurrency controls and multi-core synchronization to handle edge-case failures.
Develop portable test strategies that scale seamlessly from subsystem-level simulations to FPGA and final Silicon.
Collaborate with hardware architecture and software teams to ensure performance targets are met.
Integrate advanced automation frameworks and emerging AI-driven verification techniques into the existing lifecycle.
Identify and master unique architectural constraints of the specific SoC to push bandwidth limits further.