Design Verification Infrastructure Sr. Staff Engineer

Marvell TechnologySanta Clara, CA
$127,630 - $191,200

About The Position

Marvell's Central CAD engineering group is building a next-generation AI-integrated ASIC design verification flow. This flow utilizes a deterministic Python framework that manages build, run, verdict, coverage, and quality gates, ensuring reproducibility. An AI layer enhances this by assisting with task selection, failure triaging, and proposing fixes for human approval. The role involves designing and owning the core Python components of this framework, making them available to DV engineers.

Requirements

  • Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 3-5 years of related professional experience or Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 2-3 years of experience or equivalent professional experience in lieu of a formal degree.
  • Strong, idiomatic Python: clean, testable code and solid command-line tooling.
  • Comfort on Linux and the command line, and with Git.
  • Solid data-structures fundamentals, including graphs/DAGs.
  • Working knowledge of CI/CD.
  • Self-directed: can take a well-scoped problem and deliver a component end to end.
  • Clear written communication; the team is collaborative and distributed across time zones.

Nice To Haves

  • Hardware-verification fundamentals and exposure to SystemVerilog/UVM.
  • Hands-on with an EDA simulator — Cadence Xcelium and/or Synopsys VCS.
  • Coverage concepts: collection, merge, and closure.
  • Comfort using AI coding agents, with a habit of critically evaluating their output.
  • Exposure to MCP or other agent/tool integration.
  • Familiarity with compute-grid job scheduling (LSF, SLURM, or SGE).

Responsibilities

  • Design and own core Python framework components, including the declarative build graph and its importer, the run-record store for reproducible runs, coverage merge, and verdict logic.
  • Build the simulator backend abstraction for Cadence Xcelium (MSIE incremental elaboration) and Synopsys VCS, allowing for easy addition of new simulators.
  • Assemble self-contained, token-efficient failure bundles (waveforms, logs, run-record fields, testbench configuration, and source pointers) for debugging.
  • Integrate with compute-grid job submission, results dashboard, CI for gate-blocking changelist paths, and MCP endpoints.
  • Support the AI layer by authoring reusable agent skills and prompts, building evaluation harnesses for triage and fix quality, and enforcing deterministic guardrails.
  • Package, deploy, and operate the flow, rolling it out to verification teams and monitoring/troubleshooting in production.
  • Write documentation and reusable procedures for broader organizational adoption.

Benefits

  • Employee stock purchase plan with a 2-year look back
  • Family support programs
  • Robust mental health resources
  • Recognition and service awards
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