Design Verification Engineer

Solidigm•Rancho Cordova, CA

3d•$121,280 - $194,100•Hybrid

About The Position

This role is responsible for pre-silicon verification of advanced 3D NAND designs, including UVM-based verification, functional coverage, assertions, mixed-signal modeling and simulation, debugging, and verification-flow automation.

Requirements

Master’s degree with 3+ years of relevant experience, or bachelor’s degree with 5+ years, in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
Prior experience in pre-silicon verification of memory products is required.
Hands-on experience with UVM, SystemVerilog Assertions, and formal property verification.
Hands-on experience with mixed-signal verification, modeling, and simulation, supported by strong knowledge of digital and analog circuit design.
Strong data analysis capabilities, with the ability to communicate technical findings clearly through written reports and presentations.
Strong independent debugging and problem-solving skills, with proficiency in programming or scripting for design and verification automation.
Excellent written and verbal communication skills, with the ability to collaborate effectively across design, verification, modeling, and cross-functional teams.

Nice To Haves

memory-industry verification experience
full-chip and regression verification
code and functional coverage closure
Python, Perl, or shell scripting
AI-assisted workflows
commercial simulation, formal, and mixed-signal tools

Responsibilities

Create and maintain verification test plans based on design specifications.
Develop UVM-based directed and constrained-random tests, debug simulation failures, and quickly identify design, testbench, or test issues.
Define functional coverage models and perform coverage analysis and closure.
Create and maintain SystemVerilog Assertions (SVA) for 3D NAND designs based on verification requirements.
Develop, maintain, and enhance the UVM-based verification environment to support evolving design and verification requirements.
Develop and maintain mixed-signal full-chip models and verification environments, including analog behavioral models, cell-level testbenches, and full-chip mixed-signal netlists and testbenches.
Develop scripts and tools to automate verification workflows, regression execution, results processing, and data collection.