Design Verification Engineer

Apple•Cupertino, CA

3d•Hybrid

About The Position

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do. APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA.

Requirements

Basic semiconductor physics.
CMOS and/or VLSI Design
Computer and Processor Architecture Design
Design verification and functional coverage
Developing RTL for digital logic blocks using SystemVerilog, including linting and synthesis readiness.
Low-power techniques including clock gating, power gating, and multi-voltage designs
Experience in computer architecture specification and performance analysis, including determining initial microarchitecture specification of a design.
Object oriented programming, C, C++, System Verilog, Python, Perl, and algorithm
Parallel Computer Architecture
Test and scripting: Perl, Tcl, shell, Makefile, and Python

Responsibilities

Work with architecture and design teams to review design requirements, develop architectural specifications and check specifications for correctness.
Develop system Verilog based golden reference model to mimic the logical behaviors of RTL designs, according to the specification.
Develop system Verilog assertions and checkers for testing the RTL design.
Develop assembly language or Perl and Python based directed tests and constrained random stimulus for design features.
Run test simulations of RTL design using simulator and emulator tools.
Debug failures observed in RTL simulations and work with RTL design team on fixing the bugs.
Develop coverage constructs; collect coverage from RTL regressions and review code, functional coverage.
Involved in the formal verification of our design using jasper formal tool.
Develop manual or automated formal checks to better verify the design.
Run the checks through formal verification tool and debug any failures observed.
Develop Perl and Python scripts for automating different part of the testing environment.
Summarize failures from regressions, develop formal connectivity checks, auto file tickets from regression reports.