We are seeking a Design Verification Engineer with strong SV/UVM expertise and experience in AXI/NOC/Ethernet/PCIe/UCIe Switch. Knowledge of CPU ARM/RISC-V with C is also needed, along with experience in Regression & Coverage Closure. This role requires executing complete verification projects as a senior engineer, involving hands-on experience, mentoring, client communication, in-depth technical reviews, and tracking both technical and management aspects. The engineer will provide guidance to the team on developing UVM-based SV test-benches, defining block, sub-system, and SOC top-level test plans, and verification methodologies, flows, and quality metrics for PCIe, NVMe, NAND, DDR, and CPU sub-systems.
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Job Type
Full-time
Career Level
Senior
Education Level
Associate degree