Design Verification Engineer

Prodapt • Vancouver CN, British Columbia

10h • Onsite

About The Position

Prodapt is seeking a Senior Design Verification Engineer with 8+ years of experience to verify ASIC/SoC designs using SystemVerilog/UVM. This role involves developing automated test environments and driving bug closure throughout the development cycle for a client in Sunnyvale, CA. Prodapt is a large, fast-growing, specialized player in the Connectedness industry, recognized by Gartner, with deep expertise in transformative technologies. They are a trusted partner for enterprises across the Connectedness vertical, designing, configuring, and operating solutions for digital landscapes, network infrastructure, and business operations. Prodapt's clients connect 1.1 billion people and 5.4 billion devices and include major telecom, media, and internet firms. Prodapt is a "Great Place To Work® Certified™" company with over 6,000 employees in 30+ countries and is part of The Jhaver Group.

Requirements

• B.S or M.S degree in Electrical Engineering, Computer Engineering or Computer Science
• Hands-on experience in Verilog, SystemVerilog, C/C++ based verification, and UVM methodology
• Experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies
• Experience in EDA tools and scripting (Python, Perl, Shell) used to build tools and flows for verification environments.
• Experience in architecting and implementing Design Verification infrastructure and executing the complete verification cycle
• Strong knowledge of hardware description languages (HDLs) like Verilog or VHDL, and familiarity with simulation tools.
• Ability to analyze complex systems and troubleshoot issues effectively.
• Proficiency in programming languages such as Python, C/C++, or SystemVerilog for automation and test development.
• Excellent verbal and written communication skills to collaborate with cross-functional teams.

Nice To Haves

• Experience in the development of UVM based verification environments from scratch
• Experience with Design verification of Data-center applications like Video, AI/ML, and Networking designs
• Experience with revision control systems like Mercurial(Hg), Git or SVN
• Experience with verification of ARM/RISC-V based sub-systems or SoCs

Responsibilities

• Develop and implement verification plans that outline the testing strategy for new designs.
• Create and execute test cases, simulations, and scripts to validate designs against specifications.
• Work closely with design engineers, software developers, and other stakeholders to understand design requirements and ensure comprehensive verification coverage.
• Identify, analyze, and resolve design issues and bugs through systematic testing and debugging techniques.
• Maintain detailed documentation of verification processes, test results, and design changes.
• Contribute to the development of best practices and methodologies for design verification.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: Associate degree