Design Verification Engineer, Memory Controller

Samsung Electronics•San Jose, CA

1d•$151,000 - $251,800

About The Position

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices consumed by millions of people around the world. Come build with us! As a Design Verification Engineer, you will contribute to the verification of memory controller IPs. The ideal candidate will have a background in design verification, testbench architecture, and knowledge in methodologies across both block- and top-level environments. You will execute verification strategy, implement best practices, and support project goals in collaboration with global cross-functional teams to advance Samsung’s custom memory controller. You develop deep expertise in the micro‑architecture and verification of memory‑controller IPs, driving functional correctness, performance verification, and latency testing of high‑performance, low‑latency solutions that meet the demanding requirements of complex SoC designs. You play a role in architecting, developing, and maintaining reusable verification environments and testbenches from scratch, including stimulus, assertions, checkers, covergroups, and SystemVerilog constraints. You support design excellence and thorough verification of key features by contributing to test plans, verifying feature correctness, performing code and spec reviews, debugging functional failures from regressions to identify root cause, and performing coverage analysis to identify gaps and propose improvements. You contribute to defining new verification methodologies, improving flows and productivity, and adopting advanced practices such as power-aware verification with UPF and gate-level simulations. You collaborate with design, SoC, physical design, and performance verification teams to analyze and debug failures, resolve spec issues, and enable successful bring-up across IP, SoC, and silicon. You take initiative on moderate-to-complex projects and contribute to a high-performing team culture by communicating openly and exercising data-driven decision making. Our Team The System IP & SoC Architecture team at SARC/ACL designs proprietary coherent interconnects and memory controllers that power Exynos SoCs for Samsung’s premium consumer devices. We play a critical role in shaping the technology roadmap, delivering scalable, performance- and power-optimized IP solutions that support advanced system modeling and real-world applications such as gaming and computational photography. With scalability and efficiency at the core of our designs, our IP integrates seamlessly into complex semiconductor products, enabling cutting-edge memory subsystem capabilities across diverse market segments. Joining our team means collaborating alongside talented engineers from diverse technical backgrounds across a global organization. You’ll have the opportunity to build next-generation technologies, broaden your expertise, and solve impactful challenges in a supportive environment built on collaboration, continuous learning, and growth.

Requirements

10+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 8+ years of experience with a Master’s Degree, or 6+ years of experience with a Ph.D
8+ years of professional experience in a design verification role building testbenches from scratch
Strong background in design verification of LPDDR memory controllers, combined experience with caches and coherent interconnects is a plus
Experience with DDR/LPDDR/HBM protocols and memory model VIPs
Proficiency in ARM protocols – CHI, AXI, ACElite, APB
Strong coding skills in System Verilog, UVM
Experience with Git version control, Unix/Perl scripting
Strong communication and collaboration skills, with the ability to navigate ambiguity in a fast-paced, global team environment.

Nice To Haves

Formal verification skills will be a plus

Responsibilities

Contribute to the verification of memory controller IPs.
Execute verification strategy, implement best practices, and support project goals in collaboration with global cross-functional teams to advance Samsung’s custom memory controller.
Develop deep expertise in the micro‑architecture and verification of memory‑controller IPs, driving functional correctness, performance verification, and latency testing of high‑performance, low‑latency solutions that meet the demanding requirements of complex SoC designs.
Play a role in architecting, developing, and maintaining reusable verification environments and testbenches from scratch, including stimulus, assertions, checkers, covergroups, and SystemVerilog constraints.
Support design excellence and thorough verification of key features by contributing to test plans, verifying feature correctness, performing code and spec reviews, debugging functional failures from regressions to identify root cause, and performing coverage analysis to identify gaps and propose improvements.
Contribute to defining new verification methodologies, improving flows and productivity, and adopting advanced practices such as power-aware verification with UPF and gate-level simulations.
Collaborate with design, SoC, physical design, and performance verification teams to analyze and debug failures, resolve spec issues, and enable successful bring-up across IP, SoC, and silicon.
Take initiative on moderate-to-complex projects and contribute to a high-performing team culture by communicating openly and exercising data-driven decision making.