Design Verification Engineer IV

Arrow Electronics•San Jose, CA

1d•$112,200 - $176,000•Onsite

About The Position

This role is responsible for architecting Verification Environments for ASIC SoC and providing verification support from defining the verification plan to multi-million gate product tapeout. The engineer will also be involved in test design and development, creating complex self-checking test benches with constraint random stimulus generation, and architecting SoC test FW. This position requires a deep understanding of ASIC features and the ability to develop and debug SoC ASIC platform test FW and specific tests in C/C++. The engineer will partner in methodology development activities, actively planning, analyzing, and reviewing functional and technical specification documents. They will also implement and maintain an integrated end-to-end formal verification flow for formal verification objectives and develop/modify scripts to automate the verification process. The role involves developing the verification environment, including environment assumptions, assertions, and cover properties in the context of the verification plan. This position requires in-depth knowledge and experience, the ability to solve complex problems with a new perspective using existing solutions, and to work independently with minimal guidance. The engineer will act as a resource for colleagues with less experience and represents a level at which a career may stabilize for many years. They will use best practices and knowledge of internal or external business issues to improve products/services or processes, and often lead the work of project teams, potentially training junior staff.

Requirements

Strong SV/UVM expertise
AXI/NOC/Ethernet/PCIe/UCIe Switch expertise
CPU ARM/RISC-V with C knowledge
Regression & Coverage Closure
Requires in-depth knowledge and experience
Solves complex problems; takes a new perspective using existing solutions
Works independently; receives minimal guidance
Acts as a resource for colleagues with less experience
Represents the level at which career may stabilize for many years or even until retirement
Uses best practices and knowledge of internal or external business issues to improve products/services or processes
Often leads the work of project teams; may formally train junior staff
Works independently
Typically requires a minimum of 8 years of related experience with a 4 year degree; or 6 years and an advanced degree; or equivalent experience

Responsibilities

Architecting Verification Environments for ASIC SoC
Providing verification support from defining verification plan to multi-million gate product tapeout
Developing complex self checking test benches with constraint random stimulus generation
Architecting SoC test FW and creating test plan documentation to cover ASIC features
Developing and debugging SoC ASIC platform test FW and specific tests in C/C++
Partnering in methodology development activities
Actively planning, analyzing and reviewing functional and technical specification documents
Implementing and maintaining integrated end-to-end formal verification flow for the formal verification objective
Developing/modifying scripts to automate the verification process
Developing verification environment including environment assumptions, assertions, and cover properties in context of the verification plan