Design Verification Engineer, Coherent Interconnect

Samsung Electronics•San Jose, CA

About The Position

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices consumed by millions of people around the world. Come build with us! Role and Responsibilities As a Design Verification Engineer, you will contribute to the verification of System IP, including coherent interconnects and caches. The ideal candidate will have a background in design verification, testbench architecture, and knowledge in methodologies across both block- and top-level environments. You will execute verification strategy, implement best practices, and support project goals in collaboration with global cross-functional teams to advance Samsung’s cutting-edge coherent interconnect IPs that power next-generation consumer mobile products. You develop and maintain deep expertise in microarchitecture and design verification for coherent interconnect IPs to develop, verify, and optimize high-performance, low-latency interconnect solutions that meet the needs of complex SoC designs. You play a role in architecting, developing, and maintaining reusable verification environments and testbenches from scratch, including stimulus, assertions, checkers, covergroups, and SystemVerilog constraints. You support design excellence and thorough verification of key features by contributing to test plans, verifying feature correctness, performing code and spec reviews, debugging functional failures from regressions to identify root cause, and performing coverage analysis to identify gaps and propose improvements. You contribute to defining new verification methodologies, improving flows and productivity, and adopting advanced practices such as power-aware verification with UPF and gate-level simulations. You collaborate with design, SoC, physical design, and performance verification teams to analyze and debug failures, resolve spec issues, and enable successful bring-up across IP, SoC, and silicon. You take initiative on moderate-to-complex projects and contribute to a high-performing team culture by communicating openly and exercising data-driven decision making.

Requirements

10+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 8+ years of experience with a Master’s Degree, or 6+ years of experience with a Ph.D.
8+ years of professional experience in a design verification role building testbenches from scratch
Strong background in design verification of coherent interconnects, combined experience with LPDDR memory controllers is a plus
Proficiency in ARM protocols – CHI, AXI, ACElite, APB
Strong coding skills in System Verilog, UVM
Experience with Git version control, Unix/Perl scripting
Formal verification skills will be a plus
Strong communication and collaboration skills, with the ability to navigate ambiguity in a fast-paced, global team environment.

Responsibilities

Contribute to the verification of System IP, including coherent interconnects and caches.
Execute verification strategy, implement best practices, and support project goals in collaboration with global cross-functional teams.
Develop, verify, and optimize high-performance, low-latency interconnect solutions that meet the needs of complex SoC designs.
Architect, develop, and maintain reusable verification environments and testbenches from scratch, including stimulus, assertions, checkers, covergroups, and SystemVerilog constraints.
Support design excellence and thorough verification of key features by contributing to test plans, verifying feature correctness, performing code and spec reviews, debugging functional failures from regressions to identify root cause, and performing coverage analysis to identify gaps and propose improvements.
Contribute to defining new verification methodologies, improving flows and productivity, and adopting advanced practices such as power-aware verification with UPF and gate-level simulations.
Collaborate with design, SoC, physical design, and performance verification teams to analyze and debug failures, resolve spec issues, and enable successful bring-up across IP, SoC, and silicon.
Take initiative on moderate-to-complex projects and contribute to a high-performing team culture by communicating openly and exercising data-driven decision making.