Design Verification Engineer - Cellular Baseband

Apple • San Diego, CA

1d

About The Position

At Apple, we work to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet and changing the game? We have an opportunity for an outstandingly hardworking design verification engineer. As a member of our wide-ranging group, you will have the rare and extraordinary opportunity to craft upcoming products that will delight and inspire millions of Apple’s customers every single day. This role is for a digital-focused DV engineer who will enable us to produce fully functional first silicon for IP designs.

Requirements

• Bachelor of Science degree with meaningful experience or internships
• Deep knowledge of SystemVerilog and UVM
• Deep knowledge in developing scalable and portable test-benches
• Proven experience with verification methodologies and tools such as simulators, waveform viewers
• Build and run automation, coverage collection, gate level simulations
• Some UVM knowledge
• C/C++ level knowledge
• Deep experience with serial protocols such as PCIe or USB, parallel protocol such as DDR
• Basic knowledge of formal verification methodology
• Some experience with power-aware (UPF) or similar verification methodology
• Knowledge of one of the scripting languages such as Python, Perl, TCL

Responsibilities

• Establishing DV methodology
• Test-plan development
• Verification environment development including stimulus and checkers
• Test-writing
• Debug
• Coverage
• Sign-off for RTL freeze and tape-out
• Ensuring bug-free first silicon for part of the SoC / IP
• Developing detailed test and coverage plans based on the micro-architecture
• Developing verification methodology suitable for the IP, ensuring a scalable and portable environment
• Developing verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage
• Developing verification plans for all features under your care
• Executing verification plans, including design bring-up, DV environment bring- up, regression enabling all features under your care, and debug of the test failures
• Developing block, IP and SoC level test-benches
• Tracking and reporting DV progress using a variety of metrics, including bugs and coverage

What This Job Offers

• Job Type: Full-time
• Career Level: Entry Level