Design Verification Architect

Intel Corporation•Santa Clara, CA

1d•$190,610 - $269,100•Hybrid

About The Position

Defines, architects, and documents verification strategy and methodologies for implementing and verifying the silicon design in the most optimal manner. Architects the testbenches and develops universal verification methodology (UVM) or formal based verification approaches. Integrates the block testbench in chiplevel UVM environment and verifies integration. Develops test strategy, test bench architecture, and test plans for design blocks to conform to specifications. Enables interaction with analog and digital teams and supports postsilicon validation activities. Collaborates with the architecture and design team to create random test generation plans, runs functional simulation to identify gaps in design specification, and conducts failure analysis, coverage analysis, and closure. Defines and develops the security validation strategy and validation infrastructure to incorporate security tools and methods to improve security coverage.

Requirements

Bachelor's degree in Electronics, Computer Engineering, or related field and at least 6+ years of experience OR a Master's degree in the mentioned fields with 4+ years of experience in silicon design development, frontend validation methodologies, simulation environment development (testbench, checker), and simulation/emulation debugging.
Proficiency in functional and code coverage closures.
Expertise in hardware simulation and validation tools, with strong technical proficiency in C/C++/Python and System Verilog.
Familiarity with IP validation tools, processes, and protocols.

Nice To Haves

Experience with OVM/UVM-based test benches and formal verification tools.
Deep knowledge of graphics architecture and designs, with an understanding of microarchitectural features.
Strong team collaboration skills, problem-solving ability, and attention to detail.
Desire to work on high-impact projects that challenge and expand your technical capabilities.

Responsibilities

Defines, architects, and documents verification strategy and methodologies for implementing and verifying the silicon design in the most optimal manner.
Architects the testbenches and develops universal verification methodology (UVM) or formal based verification approaches.
Integrates the block testbench in chiplevel UVM environment and verifies integration.
Develops test strategy, test bench architecture, and test plans for design blocks to conform to specifications.
Enables interaction with analog and digital teams and supports postsilicon validation activities.
Collaborates with the architecture and design team to create random test generation plans, runs functional simulation to identify gaps in design specification, and conducts failure analysis, coverage analysis, and closure.
Defines and develops the security validation strategy and validation infrastructure to incorporate security tools and methods to improve security coverage.