Design Validation Test - Lead/Principal Engineer

Cerebras Systems•Sunnyvale, CA

4d•Onsite

About The Position

Cerebras Systems is seeking a hands-on Design Validation Test (DVT) Technical Lead (Individual Contributor) to own and drive the DVT process end-to-end across complex electrical engineering boards and full systems. This role involves defining validation strategy, building test plans and infrastructure, leading deep debug and root-cause analysis (RCA), and driving closure through design changes and re-test. The domain includes challenging power delivery technology, fast high-speed I/O, and electro-mechanical systems with thermal, optics, and high-power constraints. People management is not required, though mentoring is a plus.

Requirements

BS/MS in Electrical or Computer Engineering (or equivalent experience).
8–15+ years of hardware validation/DVT experience on complex board and system-level products.
Demonstrated ownership of board bring-up and DVT execution: test plan creation, instrumentation, debug, and closure.
Strong background in power delivery validation and measurement (sequencing, margining, droop, ripple/noise, IR drop).
Strong background in high-speed I/O validation and debug (PCIe/Ethernet-class links; channel and system-level troubleshooting).
Proficiency with lab equipment: oscilloscopes, logic analyzers, power supplies/analyzers, DC electronic loads; VNAs/BERTs as applicable.
Strong written and verbal communication; ability to present results and drive decisions with data.

Nice To Haves

Experience with rack-scale and/or liquid-cooled systems; validation in environmental chambers.
Experience supporting compliance/safety/EMC efforts as part of DVT readiness.
Python (or similar) for test automation and data analysis; experience integrating results into dashboards/CI workflows.
Experience mentoring engineers/technicians as an informal technical leader.

Responsibilities

Own DVT for complex PCBAs and subassemblies from first power-on through design sign-off, including power validation (sequencing, regulator/hotswap behavior, rail margining, DC IR drop, AC noise/ripple characterization), clock distribution validation, and high-speed I/O interface validation (e.g., Ethernet/PCIe-class links, board-to-board connectors and cabling).
Validate and debug low-speed system management interfaces (e.g., I2C/SPI/USB) and intermittent or systemic failures.
Perform stress/environmental testing (extended runtime, temperature cycling) and characterization under margined conditions.
Own system integration validation planning and execution across representative configurations and operating envelopes.
Drive readiness and execution across lab and chamber environments, including dependency management (test scripts, instrumentation, SW readiness, sample availability).
Validate and debug system-level issues spanning electrical, mechanical, thermal, and optics interactions.
Partner with reliability and manufacturing teams to ensure DVT coverage supports ramp readiness and reduces escapes.
Define a risk-based DVT strategy spanning board/subassembly engineering validation through system integration validation.
Author and maintain DVT plans, procedures, and reports with crisp pass/fail criteria and coverage rationale.
Establish stage gates and readiness reviews for execution quality (fixtures, instrumentation, scripts, SW readiness).
Build and own benchtop and rack-level validation setups that are repeatable and automation-friendly.
Lead RCA for validation failures; drive corrective actions with design teams; verify fixes through re-test and data review.
Execute and interpret power integrity/stability measurements (voltage/current stability, droop, ripple/noise, IR drop) and close gaps to requirements.
Validate high-speed interconnect performance and margin; isolate failures across channel, connector/cable, PHY, and firmware/diagnostics layers.
Partner with diagnostics/software to improve DVT throughput via scripting, logging, and standardized test stages.
Define required data capture and reporting standards to accelerate debug and support release gating.
Drive continual improvements to test coverage, efficiency, and repeatability across builds.
Align EE/ME/FW/Diagnostics/Reliability/Manufacturing on priorities, schedules, and closure criteria.
Influence design-for-testability improvements (debug visibility, margining hooks, instrumentation points, serviceability).