This role is for a Design For Test Engineer IV, responsible for scan insertion, JTAG, ATPG DRC and coverage analysis, and simulation debug with timing/SDF. The engineer will ensure the successful technical delivery of DFT deliverables to customers, debug simulation failures to find root causes, and work cross-functionally with design teams to define and implement DFT solutions. The role also involves collaborating to enhance DFT best practices within the team, including new methodologies, technologies, and tools. Additionally, the engineer will function with clients and technical teams to secure and execute concurrent objectives, envision the usage of new technology for desired results, and support the mapping of business requirements to design customized solutions using strong analytical skills to analyze business practices and define optimal procedures.
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Job Type
Full-time
Career Level
Senior