Design Engineer (7671)
About The Position
Responsible for utilizing TSMC’s leading process technology and portfolio of design enablement solutions to unleash innovation for the global semiconductor industry. In doing so, perform Design Rule Check, Layout vs. Schematic checking, and fix IDV/EMIR/Noise/SigEM violations and errors, lead the customization and implementation of top clocks and timing ECOs on high-performance blocks. Specific duties include: DRC/LVS/ERC/ANTENNA analysis and clean up; Floorplan analysis and congestion solution; Power IR/EM analysis and fix; Signal EM/Noise analysis and fix; Physical verification sign off; Implement ECOs for timing closure; and Customized Clock Tree structure.
Requirements
- Master’s degree or foreign equivalent in Electrical Engineering, Computer Science, or a related field of study
- Experience in research projects or internship related to RTL coding, digital design and testing, physical implementation or design verification
- Experience in Perl/TCL language programming
- Experience in Chip level integration, and wire editing
- Experience with complete Netlist-GDS P&R, and signoff task
- Experience in block level implementation or chip integration and signoff
- Knowledge of hardware design courses including VLSI design, digital integrated circuits, logic design, computer architecture, and digital design automation
- Knowledge of major EDA tools/design flows
- Knowledge of Low-power implementation methodology
Responsibilities
- DRC/LVS/ERC/ANTENNA analysis and clean up
- Floorplan analysis and congestion solution
- Power IR/EM analysis and fix
- Signal EM/Noise analysis and fix
- Physical verification sign off
- Implement ECOs for timing closure
- Customized Clock Tree structure
Benefits
- comprehensive benefits
- extensive development opportunities and programs
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What This Job Offers
Job Type
Full-time
Career Level
Mid Level
