Design Engineer (7672)

TSMC•San Jose, CA

50d•Onsite

About The Position

Responsible for the Design Rule Check, Layout vs. Schematic checking and fix all PDV/EMIR/Noise/SigEM violations and errors. You may also do customization and implementation of top clocks and implement timing ECOs on high performance blocks. Specific job duties include: DRC/LVS/ERC/ANTENNA analysis and clean up, Floorplan analysis and congestion solution, Power IR/EM analysis and fix, Signal EM/Noise analysis and fix, Physical verification sign off; Implement ECOs for timing closure, and Customized Clock tree structure .

Requirements

Master’s degree or foreign equivalent in Electrical Computer Engineering, Electrical Engineering, or related field
Knowledge of hardware design courses including VLSI design, digital integrated circuits, logic design, design for testing, computer architecture, and digital design automation
Knowledge of Static timing analysis, power and area estimation
Knowledge of major EDA tools/design flows using Cadence Innovus
Knowledge of advanced technology, Chip level integration, and wire editing, low-power implementation methodology
Experience in research projects or internship related to RTL coding, digital design and testing, physical implementation or design verification
Experience in TCL language programming
Experience complete Netlist-GDS P&R, signoff task
Experience in block level implementation or chip integration and signoff