Design Engineer II

Cadence Design Systems•Austin, TX

About The Position

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. This role involves RTL to GDSII implementation of in-house IP and external customer designs. The position also includes the development, automation, and maintenance of EDA flows and scripts for physical implementation. The engineer will develop TFM to optimize PPA for IPs and Soft Controllers, and perform PPA characterization and optimization of flows for performance-oriented and power-oriented best-in-class IP cores in advanced process nodes, on TSMC, Intel, Samsung, and Rapidus Foundries. The role requires digital design implementation using Cadence EDA tools such as Genus, Innovus, Conformal, Litmus, Tempus, Voltus, Certus, Pegasus, and other backend tools. Solid scripting skills including Python and Tcl are essential.

Requirements

MS/MTech/BE/ BTech in Electronics from reputed institutes with 2 + years experience
Physical design experience in ASIC design environment
Knowledge of complete ASIC Design Flow, including Synthesis, Physical Designing, Timing Analysis, Power Analysis and Formal Verification
Solid scripting skills including Python and Tcl

Nice To Haves

Excellent leadership, communication, analytical and problem solving skills
Self-motivated and good team player

Responsibilities

RTL to GDSII implementation of in-house IP and external customer designs
Development, automation and maintenance of EDA flows and scripts for physical implementation
Develop TFM to optimize PPA for IP’s and Soft Controllers
PPA characterization and optimization of flow for performance-oriented and power-oriented best-in-class IP cores in advanced process nodes, on TSMC, Intel, Samsung and Rapidus Foundries
Digital design implementation using Cadence EDA tools - Genus, Innovus, Conformal, Litmus, Tempus, Voltus, Certus, Pegasus and other backend tools