Design Engineer I
About The Position
Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at www.silabs.com. Meet the Team You’ll join the Physical Implementation Team. This team is responsible for transforming RTL designs into manufacturable silicon, driving the implementation flow from synthesis through physical design and final tapeout (GDSII). Our team works closely with Design, Verification, DFT, and Technology teams to ensure high-performance, low-power, and reliable integrated circuits are delivered on schedule. This is a great opportunity for engineers who are passionate about digital design, timing analysis, and seeing their work become real silicon.
Requirements
- Master's degree in Electrical Engineering, Computer Engineering, or a related field.
- Academic or project experience with Static Timing Analysis (STA).
- Experience developing or working with timing constraints (SDC).
- Understanding of digital IC design and implementation concepts.
- Knowledge of chip-level or block-level signoff methodologies.
- Strong analytical and problem-solving skills.
- Effective communication skills and ability to work in a collaborative team environment.
Nice To Haves
- Experience with industry-standard STA tools such as Cadence Tempus or Synopsys PrimeTime.
- Coursework, research, or project experience in digital implementation, physical design, or timing closure.
- Programming or scripting experience with Python, Perl, or Tcl.
- Familiarity with semiconductor design flows from RTL through tapeout.
- Exposure to low-power design techniques and timing optimization methodologies.
- Experience working with Linux/Unix environments and EDA tool flows.
Responsibilities
- Support the physical implementation of digital designs from RTL through GDSII/tapeout.
- Develop and maintain timing constraints (SDC) for block-level and chip-level designs.
- Perform static timing analysis (STA) to identify and resolve timing violations across multiple operating conditions.
- Assist with block-level and chip-level signoff activities, ensuring designs meet performance, power, and quality targets.
- Collaborate with cross-functional teams including Design Engineering, Verification, DFT, and CAD to drive implementation closure.
- Analyze timing reports and recommend design or constraint improvements.
- Participate in debugging and resolving implementation, timing, and design integration issues.
- Contribute to the continuous improvement of physical implementation methodologies, flows, and automation.
Benefits
- Great medical (Choice of PPO or Consumer Driven Health Plan with HSA), dental and vision plans
- Highly competitive salary
- 401k plan with match and Roth plan option
- Equity rewards (RSUs)
- Life/AD&D and disability coverage
- Flexible spending accounts
- Adoption assistance
- Back-Up childcare
- Additional benefit options (Commuter benefits, Legal benefits, Pet insurance)
- Flexible PTO schedule
- 3 paid volunteer days per year
- Tuition reimbursement
- Free downtown parking
- Onsite gym
- Monthly wellness offerings
- Free snacks
- Monthly company updates with our CEO
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What This Job Offers
Job Type
Full-time
Career Level
Entry Level
