Design Aids & Automation Engineering Professional

Computer Task Group, Inc•UNAVAILABLE, UNAVAILABLE

12d•Remote

About The Position

CTG is seeking to fill a Design Aids & Automation Engineering Professional position for our client. This role focuses primarily on test structure layouts rather than functional circuitry designs. The position involves developing test structure layouts using design automation per specified requirements, utilizing industry-standard EDA tools including the Cadence Virtuoso Design Environment and SKILL programming. Responsibilities include creating manual layout cells, developing parameterized cells (p-cells) for automation, interpreting and applying design rules, ensuring layouts pass Design Rule Checks (DRC), and collaborating with various engineering teams. The role also requires debugging and resolving layout and automation issues.

Requirements

Strong experience with the Cadence Virtuoso layout design tool (3+ years).
Experience with Cadence SKILL programming language (2+ years).
Solid understanding of physical layout concepts, technology ground rules, and semiconductor manufacturing processes.
Proven ability to debug errors and solve complex technical problems.
Strong teamwork and collaboration skills.
Fluent verbal and written English communication skills.
Minimum of 3 years of hands-on experience in semiconductor physical layout and design automation.
Bachelor’s degree in Electrical Engineering, Computer Engineering, Materials Science, or a related technical discipline, or equivalent professional experience.
Excellent verbal and written English communication skills and the ability to interact professionally with a diverse group are required.

Nice To Haves

Experience with advanced sub-micron semiconductor technology nodes.
Experience using Synopsys ICV for DRC checking.
Advanced SKILL programming experience for p-cell development and design automation.
Prior experience developing test structures or similar non-functional layout designs is strongly preferred.

Responsibilities

Develop test structure layouts using design automation per specified requirements, utilizing industry-standard EDA tools including the Cadence Virtuoso Design Environment and SKILL programming.
Create manual layout cells based on defined specifications using the Cadence Virtuoso Design Environment.
Develop parameterized cells (p-cells) to support layout automation and reusable design components.
Interpret and apply design rules and macro specifications to ensure layout intent is met.
Ensure all layouts successfully pass Design Rule Checks (DRC).
Collaborate closely with process development engineers, test structure designers, and layout technicians to deliver high-quality design enablement solutions.
Debug and resolve layout and automation issues in a collaborative, team-oriented environment.
Focus primarily on test structure layouts rather than functional circuitry designs.