Defect Reduction Engineer

Samsung Electronics•Taylor, TX

1d•$90,000 - $145,000•Onsite

About The Position

Samsung Austin Semiconductor is a world leader in advanced semiconductor technology. In this role as a Defect Reduction Engineer, you will support defect control and reduction work in a high volume 24x7 manufacturing environment, with the goal of achieving yield and performance targets. You will also support New Product Introduction (NPI) as the Defect Reduction representative, performing fab process/tool trend data and correlation analysis to identify issues and trace defects to their root cause. This role requires cross-functional collaboration and the establishment of monitoring plans for new technology introductions and existing production nodes.

Requirements

Requires a Bachelor's degree in Electrical, Chemical, Mechanical Engineering, Material Science, Chemistry, Physics or related technical fields.
5+ years of Semiconductor process engineering experience in defect monitor and reduction.
Working knowledge in SPC and DOE methodology is required

Nice To Haves

Experience in leading logic technology (45nm or below) development is strongly preferred.
Relevant experience in advanced defect inspection and review tools (bright field, dark field, e-beam, Vis-edge etc.) is strongly preferred.
Knowledge of Klarity Defect (or similar) software and its application in a semiconductor processing environment is useful.

Responsibilities

Supports defect control and reduction work in a high volume 24x7 manufacturing environment, on purpose to achieve yield and performance goals.
Supports New Product Introduction (NPI) as the Defect Reduction representative: attending meetings, presenting inline inspection strategy & methodology, supporting GPM set up, spec audits, and comparison, evaluating unit part process changes and tool spreads in terms of inline and NPW defectivity data.
Performs fab process/tool trend data and correlation analysis to identify dog tools, trace defects to root cause, and rapidly take action to prevent inline process excursions.
Works cross-functionally with YE/PIE/UP to evaluate defect data on BKMs & projects, excursion monitoring & control, SWLY reduction.
Establishes FCC (Failed Chip Count) and trend monitoring plans for new technology introductions and ramps (14nm & foundry) and existing legacy production nodes (45nm/32nm/28nm) in order to achieve yield and performance goals, and support on weekly module meetings & activities.
Respond to foundry customer requests and delivering the data & analysis to meet expectation.
Supports new technology and process transfer projects from Samsung HQ (South Korea).